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1.发明授权公开(公告)号：US09594859B1
公开(公告)日：2017-03-14
申请号：US12040730
申请日：2008-02-29
Applicant: Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
Inventor： Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
CPC classification number: G06F17/5036 , G06F9/46 , G06F17/10 , G06F17/504 , G06F17/505 , G06F17/5054 , G06F17/5072
Abstract: A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.
Abstract translation: 用于电路设计的计算机辅助设计（CAD）软件中并行化软件的系统包括计算机。 计算机被配置为并行地形成或优化多个簇。 多个群集中的每个群集包括设计中网表中的一组节点。 计算机被配置为基于迭代改进，分区或分析技术来并行地确定网表中的块的布局。
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2.发明授权Method for mapping logic design memory into physical memory devices of a programmable logic device 有权将逻辑设计存储器映射到可编程逻辑器件的物理存储器件的方法公开(公告)号：US07370291B2
公开(公告)日：2008-05-06
申请号：US11069887
申请日：2005-02-28
Applicant: Ryan Fung , Ketan Padalia
Inventor： Ryan Fung , Ketan Padalia
IPC: G06F17/50
CPC classification number: G06F17/5054
Abstract: A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.
Abstract translation: 提供了一种用于将逻辑设计存储器映射到可编程逻辑器件的物理存储器件中的方法。 在生成映射解决方案时可以考虑用户约束和物理约束。 在生成映射解决方案时，可以考虑可编程逻辑器件上的功能块布局。 可以考虑多种类型的物理存储器类型，并且可以将逻辑设计存储器映射到被确定为最合适的那些类型的物理存储器设备。 可以使用例如模拟退火来优化映射解决方案。
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3.发明申请Method for mapping logic design memory into physical memory devices of a programmable logic device 有权将逻辑设计存储器映射到可编程逻辑器件的物理存储器件的方法公开(公告)号：US20050204325A1
公开(公告)日：2005-09-15
申请号：US11069887
申请日：2005-02-28
Applicant: Ryan Fung , Ketan Padalia
Inventor： Ryan Fung , Ketan Padalia
IPC: G06F17/50
CPC classification number: G06F17/5054
Abstract: A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.
Abstract translation: 提供了一种用于将逻辑设计存储器映射到可编程逻辑器件的物理存储器件中的方法。 在生成映射解决方案时可以考虑用户约束和物理约束。 在生成映射解决方案时，可以考虑可编程逻辑器件上的功能块布局。 可以考虑多种类型的物理存储器类型，并且可以将逻辑设计存储器映射到被确定为最合适的那些类型的物理存储器设备。 可以使用例如模拟退火来优化映射解决方案。
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公开(公告)号：US08539418B1
公开(公告)日：2013-09-17
申请号：US13600371
申请日：2012-08-31
Applicant: Ketan Padalia , Ryan Fung
Inventor： Ketan Padalia , Ryan Fung
IPC: G06F17/50
CPC classification number: G06F17/5054 , G06F17/5022
Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.
Abstract translation: 用于在目标设备上设计系统的方法包括基于系统与另一系统之间的相似性来识别系统中的候选部分。 保存标准被应用于系统中的候选部分以保留以标识要保存的系统的部分。 来自另一个系统的设计结果重新用于系统中保留的部分。
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5.发明授权Method for mapping logic design memory into physical memory device of a programmable logic device 有权将逻辑设计存储器映射到可编程逻辑器件的物理存储器件的方法公开(公告)号：US06871328B1
公开(公告)日：2005-03-22
申请号：US10294836
申请日：2002-11-14
Applicant: Ryan Fung , Ketan Padalia
Inventor： Ryan Fung , Ketan Padalia
IPC: G06F17/50
CPC classification number: G06F17/5054
Abstract: A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.
Abstract translation: 提供了一种用于将逻辑设计存储器映射到可编程逻辑器件的物理存储器件中的方法。 在生成映射解决方案时可以考虑用户约束和物理约束。 在生成映射解决方案时，可以考虑可编程逻辑器件上的功能块布局。 可以考虑多种类型的物理存储器类型，并且可以将逻辑设计存储器映射到被确定为最合适的那些类型的物理存储器设备。 可以使用例如模拟退火来优化映射解决方案。
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Patent Agency Ranking
公开(公告)号：US08281274B1
公开(公告)日：2012-10-02
申请号：US12655864
申请日：2010-01-08
Applicant: Ketan Padalia , Ryan Fung
Inventor： Ketan Padalia , Ryan Fung
IPC: G06F17/50
CPC classification number: G06F17/5054 , G06F17/5022
Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.
Abstract translation: 用于在目标设备上设计系统的方法包括基于系统与另一系统之间的相似性来识别系统中的候选部分。 保存标准被应用于系统中的候选部分以保留以标识要保存的系统的部分。 来自另一个系统的设计结果重新用于系统中保留的部分。
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公开(公告)号：US08499273B1
公开(公告)日：2013-07-30
申请号：US12955521
申请日：2010-11-29
Applicant: Kimberley Anne Bozman , Ryan Fung , Vaughn Betz , David Neto , Ketan Padalia
Inventor： Kimberley Anne Bozman , Ryan Fung , Vaughn Betz , David Neto , Ketan Padalia
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5077
Abstract: Systems and techniques are described for optimizing placement and routing by providing global information during early stages of a computer aided design (CAD) flow to produce better place and route solutions. Moreover, the systems and techniques described herein use natural connectivity information inherently provided in a design hierarchy.
Abstract translation: 描述了系统和技术，用于通过在计算机辅助设计（CAD）流程的早期阶段提供全局信息来优化布局和布线，以产生更好的布局和路线解决方案。 此外，这里描述的系统和技术使用固有地提供在设计层级中的自然连接信息。
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8.发明申请Apparatus and methods for parallelizing integrated circuit computer-aided design software 审中-公开用于并行集成电路计算机辅助设计软件的装置和方法公开(公告)号：US20070192766A1
公开(公告)日：2007-08-16
申请号：US11392215
申请日：2006-03-29
Applicant: Ketan Padalia , Adrian Ludwin , Vaughn Betz , Ryan Fung
Inventor： Ketan Padalia , Adrian Ludwin , Vaughn Betz , Ryan Fung
IPC: G06F9/46
CPC classification number: G06F8/45 , G06F17/5054
Abstract: A system for providing parallelization in computer aided design (CAD) software includes a computer. The computer is configured to identify a set of tasks having local independence, and assign each task in the set of tasks to be performed in parallel. The computer is further configured to perform each task in the set of tasks.
Abstract translation: 用于在计算机辅助设计（CAD）软件中提供并行化的系统包括计算机。 计算机被配置为识别具有本地独立性的一组任务，并且将要并行执行的任务集中的每个任务分配。 计算机还被配置为在该组任务中执行每个任务。
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9.发明授权Method and apparatus for integrating signal transition time modeling during routing 有权在路由过程中整合信号转换时间建模的方法和装置公开(公告)号：US08898609B1
公开(公告)日：2014-11-25
申请号：US11488392
申请日：2006-07-18
Applicant: Vadim Gouterman , Ryan Fung
Inventor： Vadim Gouterman , Ryan Fung
IPC: G06F17/50
CPC classification number: G06F17/5077 , G06F2217/84
Abstract: A method for performing routing for a logic design includes utilizing signal transition time as a criteria for selecting resources to provide interconnection between the components of the logic design.
Abstract translation: 用于执行逻辑设计的路由的方法包括利用信号转换时间作为选择资源以提供逻辑设计的组件之间的互连的准则。
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公开(公告)号：US08232826B1
公开(公告)日：2012-07-31
申请号：US12692847
申请日：2010-01-25
Applicant: Andy Nguyen , Ling Yu , Ryan Fung
Inventor： Andy Nguyen , Ling Yu , Ryan Fung
IPC: H03H11/26
CPC classification number: H03K17/005
Abstract: A circuit with N primary outputs and a delay chain with M selection multiplexers. M can be less than N, and M is based on the number of primary outputs that simultaneously require a delayed signal from the delay chain. The N primary outputs may include core outputs and/or registers. Each of the M selection multiplexers feed directly or indirectly a subset of the N primary outputs.
Abstract translation: 具有N个主输出的电路和具有M个选择多路复用器的延迟链。 M可以小于N，M基于同时需要来自延迟链的延迟信号的主输出的数量。 N个主输出可以包括核心输出和/或寄存器。 每个M选择多路复用器直接或间接馈送N个主输出的子集。
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