公开(公告)号：US12260322B2

公开(公告)日：2025-03-25

申请号：US18479161

申请日：2023-10-02

Applicant: DEEPX CO., LTD.

Inventor： Lok Won Kim ,  Jung Boo Park ,  Seong Jin Lee

IPC: G06N3/063

Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

公开(公告)号：US12086707B2

公开(公告)日：2024-09-10

申请号：US18530909

申请日：2023-12-06

Applicant: DEEPX CO., LTD.

Inventor： Lok Won Kim ,  Seong Jin Lee ,  Jung Boo Park

IPC: G06F1/10 ,  G06F1/06 ,  G06N3/02 ,  G06N3/0464 ,  G06N3/063 ,  G06N20/00

CPC classification number: G06N3/063 ,  G06F1/06 ,  G06N3/0464

Abstract: A neural processing unit may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of groups of processing elements (PEs) including a plurality of PEs; a second circuit arranged to output a plurality of clock signals to the first circuit; a third circuit configured to measure a ratio of peak power and average power of at least the first circuit; and a fourth circuit, arranged to dynamically calibrate a phase of at least one of the plurality of clock signals of the second circuit based on the ratio of peak power and average power measured in the third circuit.

公开(公告)号：US11954586B2

公开(公告)日：2024-04-09

申请号：US18459605

申请日：2023-09-01

Applicant: DEEPX CO., LTD.

Inventor： Seong Jin Lee ,  Jung Boo Park ,  Lok Won Kim

IPC: G06N3/06 ,  G06N3/063

CPC classification number: G06N3/063

Abstract: A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.

公开(公告)号：US11893477B2

公开(公告)日：2024-02-06

申请号：US18353404

申请日：2023-07-17

Applicant: DEEPX CO., LTD.

Inventor： Lok Won Kim ,  Jung Boo Park ,  Seong Jin Lee

IPC: G06N3/06 ,  G06N3/063

CPC classification number: G06N3/063

Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.