Memory system of artificial neural network based on artificial neural network data locality

    公开(公告)号:US12235778B2

    公开(公告)日:2025-02-25

    申请号:US17430323

    申请日:2020-12-03

    Inventor: Lok Won Kim

    Abstract: An artificial neural network memory system includes at least one processor configured to generate a data access request corresponding to an artificial neural network operation; and at least one artificial neural network memory controller configured to sequentially record the data access request to generate an artificial neural network data locality pattern of the artificial neural network operation and generate an advance data access request which predicts a next data access request of the data access request generated by the at least one processor based on the artificial neural network data locality pattern.

    Method for artificial neural network and neural processing unit

    公开(公告)号:US12198038B2

    公开(公告)日:2025-01-14

    申请号:US17560270

    申请日:2021-12-23

    Inventor: Lok Won Kim

    Abstract: A method performs a plurality of operations on an artificial neural network (ANN). The plurality of operations includes storing in at least one memory a set of weights, at least a portion of a first batch channel of a plurality of batch channels, and at least a portion of a second batch channel of the plurality of batch channels; and calculating the at least a portion of the first batch channel and the at least a portion of the second batch channel by the set of weights. A batch mode, configured to process a plurality of input channels, can determine the operation sequence in which the on-chip memory and/or internal memory stores and computes the parameters of the ANN. Even if the number of input channels increases, processing may be performed with one neural processing unit including a memory configured in consideration of a plurality of input channels.

    NPU capable of testing component therein during runtime

    公开(公告)号:US11651835B1

    公开(公告)日:2023-05-16

    申请号:US17886463

    申请日:2022-08-12

    CPC classification number: G11C29/78 G11C29/10

    Abstract: A neural processing unit (NPU) for testing a component during runtime is provided. The NPU may include a plurality of functional components including a first functional component and a second functional component. At least one of the plurality of functional components may be driven for calculation of an artificial neural network. Another one of the plurality of functional components may be selected as a component under test (CUT). A scan test may be performed on the at least one functional component selected as the CUT. A tester for detecting a defect of an NPU is also provided. The tester may include a component tester configured to communicate with at least one functional component of the NPU, select the at least one functional component as a CUT, and perform a scan test for the selected CUT.

    Memory controller, processor and system for artificial neural network

    公开(公告)号:US12169642B2

    公开(公告)日:2024-12-17

    申请号:US18425102

    申请日:2024-01-29

    Inventor: Lok Won Kim

    Abstract: According to an example of the present disclosure, a system is provided. A system may include a processor configured to output a memory control signal including an artificial neural network data locality, and a memory controller configured to receive the memory control signal from the processor and control a main memory in which data of an artificial neural network model corresponding to the artificial neural network data locality, is stored.

    Memory controller, processor and system for artificial neural network

    公开(公告)号:US11922051B2

    公开(公告)日:2024-03-05

    申请号:US17513913

    申请日:2021-10-29

    Inventor: Lok Won Kim

    CPC classification number: G06F3/0655 G06F3/0604 G06F3/0679 G06N3/063

    Abstract: A system for an artificial neural network (ANN) includes a processor configured to output a memory control signal including an ANN data locality; a main memory in which data of an ANN model corresponding to the ANN data locality is stored; and a memory controller configured to receive the memory control signal from the processor and to control the main memory based on the memory control signal. The memory controller may be further configured to control, based on the memory control signal, a read or write operation of data of the main memory required for operation of the artificial neural network. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

    Method for image stabilization based on artificial intelligence and camera module therefor

    公开(公告)号:US11750927B2

    公开(公告)日:2023-09-05

    申请号:US17885569

    申请日:2022-08-11

    Abstract: A method for stabilizing an image based on artificial intelligence includes acquiring tremor detection data with respect to the image, the tremor detection data acquired from two or more sensors; outputting stabilization data for compensating for an image shaking, the stabilization data outputted using an artificial neural network (ANN) model trained to output the stabilization data based on the tremor detection data; and compensating for the image shaking using the stabilization data. A camera module includes a lens; an image sensor to output an image captured through the lens; two or more sensors to output tremor detection data with respect to the image; a controller to output stabilization data based on the tremor detection data using an ANN model; and a stabilization unit to compensate for an image shaking using the stabilization data. The ANN model is trained to output the stabilization data based on the tremor detection data.

    System-on-chip and method for testing component in system during runtime

    公开(公告)号:US11669422B2

    公开(公告)日:2023-06-06

    申请号:US17499871

    申请日:2021-10-13

    Inventor: Lok Won Kim

    CPC classification number: G06F11/273 G06N3/02 G06F2213/0038

    Abstract: A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.

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