公开(公告)号：US12117866B2

公开(公告)日：2024-10-15

申请号：US18473746

申请日：2023-09-25

Applicant: DEEPX CO., LTD.

Inventor： Lok Won Kim ,  Jin Gun Song ,  Seong Jin Lee

IPC: G06F1/08 ,  G06F15/80

CPC classification number: G06F1/08 ,  G06F15/80

Abstract: A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

公开(公告)号：US12086096B2

公开(公告)日：2024-09-10

申请号：US18601598

申请日：2024-03-11

Applicant: DEEPX CO., LTD.

Inventor： Lok Won Kim ,  Seong Jin Lee ,  Jin Gun Song

IPC: G06F15/80 ,  G06F1/08

CPC classification number: G06F15/80 ,  G06F1/08

Abstract: A neural processing unit (NPU) is proposed. The NPU may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of processing elements (PE) groups including a plurality of PEs, and a second circuit configured to operate as a clock divider configured to generate a plurality of clock signals having different phases, respectively, by dividing a source clock signal and provide the plurality of clock signals to the plurality of PE groups. A first clock signal of the plurality of clock signals may be provided to a first PE group of the plurality of PE groups, and a second clock signal of the plurality of clock signals may be provided to a second PE group of the plurality of PE groups.

公开(公告)号：US11954587B2

公开(公告)日：2024-04-09

申请号：US18473777

申请日：2023-09-25

Applicant: DEEPX CO., LTD.

Inventor： Seong Jin Lee ,  Jin Gun Song ,  Lok Won Kim

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.