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公开(公告)号：US11190890B2
公开(公告)日：2021-11-30
申请号：US16500157
申请日：2017-04-12
发明人： Aleksey Khenkin , Kevin Stoddart , Gordon Cowan , Keith Getz
摘要： An acoustic testing apparatus may include connections for multiple devices under test (DUTs) to support simultaneous testing of two or more miniature electroacoustic devices. The acoustic testing apparatus may allow the testing of multiple DUTs with a ratio of less than one reference microphone per DUT. Thus, the speed of testing DUTs may be increased without adding significant cost through additional reference microphones. For example, a single reference microphone may be used to test two or four DUTs coupled together through an acoustic test cavity.
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公开(公告)号：US10080084B2
公开(公告)日：2018-09-18
申请号：US15198809
申请日：2016-06-30
CPC分类号： H04R3/06 , H04R29/004 , H04R2201/003
摘要： In accordance with embodiments of the present disclosure, a system may include a digital correcting network for correcting for an intrinsic highpass filter of a microelectromechanical systems (MEMS) microphone such that a combined phase and magnitude response of a cascade of the intrinsic highpass filter and the digital correcting network substantially approximates the response of a target highpass filter.
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公开(公告)号：US20240238842A1
公开(公告)日：2024-07-18
申请号：US18098396
申请日：2023-01-18
发明人： Marco Janko , Jorge Reynaga , Chin Yong , Eric Lindemann , Emmanuel Marchais , Hamid Sepehr , Vadim Konradi , Michael Kurek , Filippo Rossi , Anil Lal , Aleksey Khenkin
CPC分类号： B06B1/0276 , H04R29/00 , B06B2201/40
摘要： A method includes applying a high frequency signal to an electromechanical actuator and measuring a first response of the electromechanical actuator to the high frequency signal, estimating electrical parameters of the electromechanical actuator based on the first response, applying a low frequency broadband signal to the electromechanical actuator and measuring a second response of the electromechanical actuator to the low frequency broadband signal, and estimating mechanical parameters of the electromechanical actuator based on the second response and the estimated electrical parameters.
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公开(公告)号：US11942468B2
公开(公告)日：2024-03-26
申请号：US17303251
申请日：2021-05-25
CPC分类号： H01L27/0207 , H01L21/78 , H01L23/49816 , H01L23/66 , H03F3/187 , H03F3/45475 , H01L2223/6644 , H03F2200/03
摘要： A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.
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公开(公告)号：US20210120352A1
公开(公告)日：2021-04-22
申请号：US16500157
申请日：2017-04-12
发明人： Aleksey Khenkin , Kevin Stoddart , Gordon Cowan , Keith Getz
摘要： An acoustic testing apparatus may include connections for multiple devices under test (DUTs) to support simultaneous testing of two or more miniature electroacoustic devices. The acoustic testing apparatus may allow the testing of multiple DUTs with a ratio of less than one reference microphone per DUT. Thus, the speed of testing DUTs may be increased without adding significant cost through additional reference microphones. For example, a single reference microphone may be used to test two or four DUTs coupled together through an acoustic test cavity.
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6.发明公开公开(公告)号：US20240361356A1
公开(公告)日：2024-10-31
申请号：US18140456
申请日：2023-04-27
发明人： Aleksey Khenkin , Michael J. Murphy
CPC分类号： G01R1/203 , G01R19/0092
摘要： A thin-film resistor circuit for an integrated circuit provides low resistance by segmenting a thin-film resistor to provide a wider effective thin-film resistor in a smaller die. The die includes a substrate, multiple electronic devices integrated on the substrate and interconnected to form at least a portion of an electronic circuit, a plurality of interconnect lands arranged in a grid that interconnect the devices with external terminals, and a thin-film resistor implemented by two or more thin-film resistor segments that operate in parallel in the circuit. The segments are disposed between different pairs of adjacent columns of the grid interconnect lands, with one of the thin-film resistor segments electrically connected along its width to lands of a first column of the grid of interconnect lands, and another one of the thin-film resistor segments is electrically connected along its width to lands of a second column of the grid interconnect lands.
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公开(公告)号：US20240136105A1
公开(公告)日：2024-04-25
申请号：US18383816
申请日：2023-10-25
发明人： Aleksey Khenkin , David Patten , Jun Yan
CPC分类号： H01F27/2804 , H01F17/0013 , H01F27/24 , H01F41/08
摘要： A method for constructing a solenoid inductor of an IC package with active/passive devices includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.
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公开(公告)号：US11662821B2
公开(公告)日：2023-05-30
申请号：US16850904
申请日：2020-04-16
发明人： Aleksey Khenkin , Jun Yan , Marco Janko , Michael McKnight
IPC分类号： G06F3/01 , G01R33/028 , H02N11/00 , H02N2/14 , H02N1/00 , H01L41/04 , H01L41/09 , H01L41/083
CPC分类号： G06F3/016 , G01R33/028 , H02N1/006 , H02N2/14 , H02N2/142 , H02N11/00 , H01L41/042 , H01L41/083 , H01L41/09
摘要： A method may include measuring an electrical parameter of an electromagnetic load having a moving mass during the absence of a driving signal actively driving the electromagnetic load, measuring a mechanical parameter of mechanical motion of a host device comprising the electromagnetic load, correlating a relationship between the mechanical parameter and the electrical parameter, and calibrating the electromagnetic load across a plurality of mechanical motion conditions based on the relationship.
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公开(公告)号：US20220384413A1
公开(公告)日：2022-12-01
申请号：US17303251
申请日：2021-05-25
摘要： A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.
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