公开(公告)号：US20120104569A1

公开(公告)日：2012-05-03

申请号：US13025763

申请日：2011-02-11

Applicant: Chung-Hui CHEN

Inventor： Chung-Hui CHEN

IPC: H01L23/552 ,  H01L21/768

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.

Abstract translation: 集成电路包括沿第一方向布线的信号线。 第一屏蔽图案基本上与信号线平行设置。 第一屏蔽图案具有具有第一尺寸的第一边缘和具有第二尺寸的第二边缘。 第一边缘基本上与信号线平行。 第一个维度大于第二个维度。 第二屏蔽图案基本上与信号线平行设置。 第二屏蔽图案具有具有第三尺寸的第三边缘和具有第四尺寸的第四边缘。 第三边缘基本上与信号线平行。 第三维度大于第四维度。 第四个边缘面向第二个边缘。 第一空间在第二和第四边之间。

公开(公告)号：US20130193499A1

公开(公告)日：2013-08-01

申请号：US13362411

申请日：2012-01-31

Applicant: Chung-Hui CHEN

Inventor： Chung-Hui CHEN

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L27/0629 ,  H01L27/0207 ,  H01L27/0811 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.

Abstract translation: 一种器件包括具有第一掺杂剂类型的第一和第二注入区的半导体衬底。 栅极绝缘层和栅电极设置在第一和第二植入区域之间的电阻器区域的上方。 第一介电层位于第一注入区上。 提供一种接触结构，包括与门电极导电接触的第一接触部分，第一接触部分的至少一部分直接在栅电极上。 第二接触部分直接接触第一接触部分并直接形成在第一介电层上。 第三接触部分形成在第二植入区域上。

公开(公告)号：US20130185689A1

公开(公告)日：2013-07-18

申请号：US13352738

申请日：2012-01-18

Applicant: Chien-Hung CHEN ,  Yung-Chow PENG ,  Chung-Hui CHEN ,  Chih Ming YANG

Inventor： Chien-Hung CHEN ,  Yung-Chow PENG ,  Chung-Hui CHEN ,  Chih Ming YANG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/12 ,  H01L27/0207 ,  H01L29/94

Abstract: A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.

Abstract translation: 根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部 。 对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。 在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

公开(公告)号：US20130175589A1

公开(公告)日：2013-07-11

申请号：US13344137

申请日：2012-01-05

Applicant: Chung-Hui CHEN

Inventor： Chung-Hui CHEN

IPC: H01L27/06 ,  H01L21/02

CPC classification number: H01L27/067 ,  H01L21/76224 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L28/40 ,  H01L28/88 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/73 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.

公开(公告)号：US20130200449A1

公开(公告)日：2013-08-08

申请号：US13368027

申请日：2012-02-07

Applicant: Chung-Hui CHEN

Inventor： Chung-Hui CHEN

IPC: H01L27/06 ,  H01L21/336

CPC classification number: H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/6681

Abstract: A semiconductor device including field-effect transistors (finFETs) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin. The edge fins may be floating, connected to a potential source, or serve as a part of a decoupling capacitor.

Abstract translation: 一种半导体器件，包括形成在硅衬底上的场效晶体管（finFET）。 该装置包括多个有效区域，每个有效区域具有分开成规则翅片和至少一个边缘翅片的数个等间隔的翅片，规则散热片上的栅极结构以及漏极区域以及与该区域电连接的源极区域 规则散热片并与至少一个边缘鳍片断开。 边缘鳍片可以浮动，连接到电位源，或者用作去耦电容器的一部分。

公开(公告)号：US20130147057A1

公开(公告)日：2013-06-13

申请号：US13324405

申请日：2011-12-13

Applicant: Jaw-Juinn HORNG ,  Chia-Lin YU ,  Chung-Hui CHEN ,  Der-Chyang YEH ,  Yung-Chow PENG

Inventor： Jaw-Juinn HORNG ,  Chia-Lin YU ,  Chung-Hui CHEN ,  Der-Chyang YEH ,  Yung-Chow PENG

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

Abstract translation: 提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。 隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。 周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

公开(公告)号：US20130307516A1

公开(公告)日：2013-11-21

申请号：US13472063

申请日：2012-05-15

Applicant: Jaw-Juinn HORNG ,  Kuo-Feng YU ,  Chung-Hui CHEN

Inventor： Jaw-Juinn HORNG ,  Kuo-Feng YU ,  Chung-Hui CHEN

IPC: G05F3/02

CPC classification number: G05F3/16 ,  G05F3/30

Abstract: A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage.

Abstract translation: 一种带隙参考电路，包括两组双极结型晶体管（BJT）。 配置为以并联布置电连接的第一组两个或更多个BJT。 第一组BJT被配置为产生与绝对温度（PTAT）信号成比例的第一比例。 第二组两个或多个BJT被配置为以并联布置电连接。 第二组BJT被配置为产生第二PTAT信号。 一种被配置为电连接到第一组BJT和第二组BJT的电路。 电路被配置为组合第一PTAT信号和第二PTAT信号以产生参考电压。

公开(公告)号：US20130181269A1

公开(公告)日：2013-07-18

申请号：US13349723

申请日：2012-01-13

Applicant: Chung-Hui CHEN

Inventor： Chung-Hui CHEN

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L29/94 ,  H01L23/5223 ,  H01L27/0288 ,  H01L27/0629

Abstract: A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant.

Abstract translation: 一种器件包括具有第一和第二注入区域的半导体衬底以及位于第一和第二注入区之间且位于第一和第二注入区之间的电极。 接触结构与第一和第二注入区域和电极直接接触。 第三注入区域具有不同于第一掺杂剂类型的第二掺杂剂类型。 在第三植入物上提供体接触。

公开(公告)号：US20130169339A1

公开(公告)日：2013-07-04

申请号：US13341380

申请日：2011-12-30

Applicant: Chung-Hui CHEN

Inventor： Chung-Hui CHEN

IPC: H03L5/00

CPC classification number: H03K3/356113

Abstract: A level shifting circuit includes a first circuit, a second circuit and an output voltage controlling circuit. The first circuit is coupled to an input node, an output node and a first supply voltage node and configured to pull an output voltage at the output node toward the first supply voltage in accordance with an input voltage applied to the input node. The second circuit is coupled to the first circuit, the output node and the second supply voltage node and configured to pull the output voltage toward the second supply voltage in accordance with the input voltage from the first circuit. The output voltage controlling circuit is coupled to the output node and configured to control the output voltage within a range narrower than a range from the first voltage to the second voltage.

Abstract translation: 电平移位电路包括第一电路，第二电路和输出电压控制电路。 第一电路耦合到输入节点，输出节点和第一电源电压节点，并且被配置为根据施加到输入节点的输入电压将输出节点处的输出电压拉向第一电源电压。 第二电路耦合到第一电路，输出节点和第二电源电压节点，并且被配置为根据来自第一电路的输入电压将输出电压拉向第二电源电压。 输出电压控制电路耦合到输出节点并被配置为在比从第一电压到第二电压的范围窄的范围内控制输出电压。

公开(公告)号：US20120092066A1

公开(公告)日：2012-04-19

申请号：US13028790

申请日：2011-02-16

Applicant: Chung-Hui CHEN

Inventor： Chung-Hui CHEN

IPC: H01L27/092

CPC classification number: H01L29/78 ,  H01L25/00 ,  H01L27/092 ,  H01L2224/16225

Abstract: An integrated circuit includes a first pass gate and a first receiver electrically coupled with the first pass gate. The first receiver includes a first N-type transistor. A first gate of the first N-type transistor is electrically coupled with the first pass gate. A first P-type bulk of the first N-type transistor is surrounded by a first N-type doped region. The first N-type doped region is surrounded by a first N-type well. The first N-type doped region has a dopant concentration higher than that of the first N-type well.

Abstract translation: 集成电路包括第一通道栅极和与第一栅极电耦合的第一接收器。 第一接收器包括第一N型晶体管。 第一N型晶体管的第一栅极与第一栅极电耦合。 第一N型晶体管的第一P型体被第一N型掺杂区包围。 第一N型掺杂区被第一N型阱围绕。 第一N型掺杂区域的掺杂浓度高于第一N型阱的掺杂浓度。