公开(公告)号：US08588244B2

公开(公告)日：2013-11-19

申请号：US13270760

申请日：2011-10-11

Applicant: Shridhar Mubaraq Mishra ,  Tina Zhang ,  Chunfeng Hu ,  Hak Keong Sim

Inventor： Shridhar Mubaraq Mishra ,  Tina Zhang ,  Chunfeng Hu ,  Hak Keong Sim

IPC: H04L12/28

CPC classification number: H04L49/352 ,  H04L49/30 ,  H04L49/65

Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.

Abstract translation: 以太网交换机具有至少一个入口/出口，其可以以两种模式操作，在第一模式中作为GE端口，在第二模式中可操作为多个FE端口。 该端口具有8个MAC接口，每个MAC接口能够接收/发送FE报文，并且至少一个MAC接口可以配置为接收/发送GE报文。 因此，端口具有两种操作模式。 该端口还包括接收和发送模块，接收GE和FE数据包，并将GE和FE数据包发送到接口。

公开(公告)号：US20090240847A1

公开(公告)日：2009-09-24

申请号：US12051275

申请日：2008-03-19

Applicant: Chunfeng Hu

Inventor： Chunfeng Hu

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/08 ,  G06F2212/251 ,  G06F2212/253

Abstract: Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.

Abstract translation: 通过将从外围设备读取的数据响应于嵌入式系统外部的存储器的事件写入嵌入式系统中的数据。 数据或数据的一部分被复制到嵌入式系统内部的存储器中。 跟踪数据的哪一部分存储在外部存储器和内部存储器中。 通过嵌入式系统中包括的处理器从内部存储器检索复制的数据。 处理器在逻辑上和物理上与内部存储器分离一个或多个高速缓存。 处理器使用其检索的复制数据开始服务事件。

公开(公告)号：US20080089351A1

公开(公告)日：2008-04-17

申请号：US11580509

申请日：2006-10-13

Applicant: Chunfeng Hu

Inventor： Chunfeng Hu

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L47/12 ,  H04L47/2441 ,  H04L47/266 ,  H04L47/30 ,  H04L47/35 ,  H04L47/50 ,  H04L47/52 ,  H04L47/6215

Abstract: A communications queue controller for a communications network, the queue controller having a plurality of queue buffers of differing priorities. Each queue buffer has a flow control selector controllable by a programmable bit.

Abstract translation: 一种用于通信网络的通信队列控制器，所述队列控制器具有不同优先级的多个队列缓冲器。 每个队列缓冲器具有可由可编程位控制的流量控制选择器。

公开(公告)号：US20120151103A1

公开(公告)日：2012-06-14

申请号：US13372517

申请日：2012-02-14

Applicant: Chunfeng Hu

Inventor： Chunfeng Hu

IPC: G06F13/28

CPC classification number: G06F12/08 ,  G06F2212/251 ,  G06F2212/253

Abstract: Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.

Abstract translation: 通过将从外围设备读取的数据响应于嵌入式系统外部的存储器的事件写入嵌入式系统中的数据。 数据或数据的一部分被复制到嵌入式系统内部的存储器中。 跟踪数据的哪一部分存储在外部存储器和内部存储器中。 通过嵌入式系统中包括的处理器从内部存储器检索复制的数据。 处理器在逻辑上和物理上与内部存储器分离一个或多个高速缓存。 处理器使用其检索的复制数据开始服务事件。

公开(公告)号：US08095702B2

公开(公告)日：2012-01-10

申请号：US12051275

申请日：2008-03-19

Applicant: Chunfeng Hu

Inventor： Chunfeng Hu

IPC: G06F13/14

CPC classification number: G06F12/08 ,  G06F2212/251 ,  G06F2212/253

Abstract: Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.

Abstract translation: 通过将从外围设备读取的数据响应于嵌入式系统外部的存储器的事件写入嵌入式系统中的数据。 数据或数据的一部分被复制到嵌入式系统内部的存储器中。 跟踪数据的哪一部分存储在外部存储器和内部存储器中。 通过嵌入式系统中包括的处理器从内部存储器检索复制的数据。 处理器在逻辑上和物理上与内部存储器分离一个或多个高速缓存。 处理器使用其检索的复制数据开始服务事件。

公开(公告)号：US07710979B2

公开(公告)日：2010-05-04

申请号：US10987436

申请日：2004-11-12

Applicant: Ingo Volkening ,  Jiaxiang Shi ,  Chunfeng Hu

Inventor： Ingo Volkening ,  Jiaxiang Shi ,  Chunfeng Hu

IPC: H04L12/56

CPC classification number: H04L12/5601 ,  H04L12/2856 ,  H04L12/2865 ,  H04L2012/5606 ,  H04L2012/5624

Abstract: There is provided an apparatus and method for ATM bonding. The apparatus comprises a first unit having a first xDSL line connected thereto, a second unit having a second xDSL line connected thereto and a connection between the first unit and the second unit. The first unit is arranged to convert one incoming ATM datastream to a plurality of data and to convert a plurality of incoming data to one ATM data stream. The first unit is arranged to implement the ATM bonding layer of the ATM protocol. The second unit may be arranged to implement one or more of the higher layers. The method comprises the steps of: a first unit receiving an ATM data stream; the first unit converting the ATM data stream into a plurality of data; the first unit transmitting a first one of the plurality of data over a first xDSL line connected to the first unit; the first unit sending a second one of the plurality of data to a second unit via a connection; and the second unit transmitting the second one of the plurality of data over a second xDSL line connected to the second unit.

Abstract translation: 提供了一种ATM绑定的装置和方法。 该装置包括具有连接到其上的第一xDSL线的第一单元，具有连接到其上的第二xDSL线的第二单元和第一单元与第二单元之间的连接。 第一单元被布置成将一个输入的ATM数据流转换成多个数据并将多个输入数据转换成一个ATM数据流。 第一单元被布置成实现ATM协议的ATM绑定层。 第二单元可以被布置成实现一个或多个较高层。 该方法包括以下步骤：接收ATM数据流的第一单元; 第一单元将ATM数据流转换成多个数据; 所述第一单元通过连接到所述第一单元的第一xDSL线发送所述多个数据中的第一数据; 所述第一单元经由连接将所述多个数据中的第二数据发送到第二单元; 并且所述第二单元通过连接到所述第二单元的第二xDSL线发送所述多个数据中的第二数据。

公开(公告)号：US09239787B2

公开(公告)日：2016-01-19

申请号：US13315763

申请日：2011-12-09

Applicant: Chunfeng Hu

Inventor： Chunfeng Hu

IPC: G06F5/00 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F12/08 ,  G06F2212/251 ,  G06F2212/253

Abstract: A system includes an internal memory configured to store data, a memory access controller, logic, and a processor. The memory access controller is operable to read data from a peripheral device in response to an event external to the system, write the data to memory external to the system and forward the data or a portion of the data to the internal memory. The logic is operable to track which portion of the data is stored in both the external memory and the internal memory. The processor has one or more caches logically and physically separated from the internal memory. The processor is operable to retrieve the data forwarded to the internal memory and use the retrieved data to begin servicing the event.

Abstract translation: 系统包括被配置为存储数据的内部存储器，存储器存取控制器，逻辑和处理器。 存储器访问控制器可操作以响应于系统外部的事件从外围设备读取数据，将数据写入系统外部的存储器，并将数据或一部分数据转发到内部存储器。 逻辑可操作以跟踪数据的哪一部分存储在外部存储器和内部存储器中。 处理器在逻辑上和物理上与内部存储器分离一个或多个高速缓存。 处理器可操作地检索转发到内部存储器的数据，并使用所检索的数据来开始服务事件。

公开(公告)号：US20130052438A1

公开(公告)日：2013-02-28

申请号：US13661756

申请日：2012-10-26

Applicant: Chunfeng Hu ,  Salvatore Grasso ,  Yoshio Sakka ,  Hidehiko Tanaka ,  Tohru Suzuki

Inventor： Chunfeng Hu ,  Salvatore Grasso ,  Yoshio Sakka ,  Hidehiko Tanaka ,  Tohru Suzuki

IPC: C04B35/515 ,  B29C67/04

CPC classification number: C04B35/5615 ,  C04B35/5603 ,  C04B35/5607 ,  C04B35/5611 ,  C04B35/5618 ,  C04B35/58007 ,  C04B35/58014 ,  C04B35/6262 ,  C04B35/6263 ,  C04B35/6264 ,  C04B35/63424 ,  C04B35/63444 ,  C04B35/6455 ,  C04B2235/3839 ,  C04B2235/3843 ,  C04B2235/5409 ,  C04B2235/5445 ,  C04B2235/6027 ,  C04B2235/604 ,  C04B2235/605 ,  C04B2235/6562 ,  C04B2235/6567 ,  C04B2235/6581 ,  C04B2235/666 ,  C04B2235/77 ,  C04B2235/78 ,  C04B2235/80 ,  C04B2235/96 ,  Y10T428/2495

Abstract: An oriented ceramic containing an Mn+1AXn phase, where the Mn+1AXn phase is a ternary compound, and M is an early transition metal, A is an A group element, X is C or N, and n is an integer of 1 to 3, wherein the oriented ceramic has a layered microstructure similar to shell layers of pearl, which is formed by laminating a layer of a nano-order to milli-order in a thickness thereof, and the oriented ceramic is an oriented bulk material a total thickness of which is in milli-order or larger at smallest.

Abstract translation: 含有Mn + 1AXn相的取向陶瓷，Mn + 1AXn相为三元化合物，M为早期过渡金属，A为A族元素，X为C或N，n为1〜 如图3所示，其中取向陶瓷具有类似于珍珠壳层的层状微结构，其通过在其厚度上层叠纳米级至毫级的层而形成，并且取向陶瓷是取向的散装材料，总厚度 其最小值为毫数或更大。

公开(公告)号：US20120069848A1

公开(公告)日：2012-03-22

申请号：US13270760

申请日：2011-10-11

Applicant: Shridhar Mubaraq Mishra ,  Tina Zhang ,  Chunfeng Hu ,  Hak Keong Sim

Inventor： Shridhar Mubaraq Mishra ,  Tina Zhang ,  Chunfeng Hu ,  Hak Keong Sim

IPC: H04L12/56

CPC classification number: H04L49/352 ,  H04L49/30 ,  H04L49/65

Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.

Abstract translation: 以太网交换机具有至少一个入口/出口，其可以以两种模式操作，在第一模式中作为GE端口，在第二模式中可操作为多个FE端口。 该端口具有8个MAC接口，每个MAC接口能够接收/发送FE报文，并且至少一个MAC接口可以配置为接收/发送GE报文。 因此，端口具有两种操作模式。 该端口还包括接收和发送模块，接收GE和FE数据包，并将GE和FE数据包发送到接口。

公开(公告)号：US07616662B2

公开(公告)日：2009-11-10

申请号：US10526992

申请日：2002-09-06

Applicant: Shridhar Mubaraq Mishra ,  Chunfeng Hu

Inventor： Shridhar Mubaraq Mishra ,  Chunfeng Hu

IPC: H04J3/24

CPC classification number: H04L49/351 ,  H04L12/46 ,  H04L12/4641 ,  H04L49/354 ,  H04L69/22

Abstract: A parser system is arranged to receive a data stream (1) having interleaved sections derived from a plurality of different packets, and to extract data from each section as it arrives. The parser system has a scanning section which receives information about each of the sections of data defining which packet it relates to, and employs this information and the properties of the data stream, to identify the locations of layer (2), layer (3) and layer (4) data. This information is passed to parser units (7), (9) which extract data based on this data and also offsets. The offsets for the parser (7) are stored in user-programmable registers (9).

Abstract translation: 解析器系统被布置为接收具有从多个不同分组导出的交织部分的数据流（1），并且在每个部分到达时提取数据。 解析器系统具有扫描部分，其接收关于定义与其相关的哪个分组的每个数据部分的信息，并且使用该信息和数据流的属性来识别层（2），层（3）的位置， 和层（4）数据。 该信息被传递给分析器单元（7），（9），其基于该数据提取数据并且还偏移。 解析器（7）的偏移量存储在用户可编程寄存器（9）中。