公开(公告)号：US08612667B2

公开(公告)日：2013-12-17

申请号：US12647555

申请日：2009-12-28

Applicant: Ching-Hui Lin ,  Kuo-Liang Yeh ,  Ken-Fu Hsu

Inventor： Ching-Hui Lin ,  Kuo-Liang Yeh ,  Ken-Fu Hsu

IPC: G06F12/00

CPC classification number: G11C29/02 ,  G11C7/1006 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management.

Abstract translation: 用于执行关于由闪存的控制器访问的数据的数据模式管理的方法包括：当控制器接收到写命令时，生成第一随机函数，其中写命令用于指示控制器将数据写入闪存 记忆; 并且逐位地调整数据的多个比特以产生伪随机比特序列，并将伪随机比特序列写入闪速存储器以表示数据，从而调整数据的数据模式分布。 还提供了一种相关联的存储器件及其控制器，其中控制器包括：ROM，被布置为存储程序代码; 布置成执行程序代码以控制对闪存的访问并管理多个块的微处理器; 以及布置成生成随机函数的随机发生器。 控制器可以执行数据模式管理。

公开(公告)号：US20110016263A1

公开(公告)日：2011-01-20

申请号：US12647555

申请日：2009-12-28

Applicant: Ching-Hui Lin ,  Kuo-Liang Yeh ,  Ken-Fu Hsu

Inventor： Ching-Hui Lin ,  Kuo-Liang Yeh ,  Ken-Fu Hsu

IPC: G06F12/02

CPC classification number: G11C29/02 ,  G11C7/1006 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management.

Abstract translation: 用于执行关于由闪存的控制器访问的数据的数据模式管理的方法包括：当控制器接收到写命令时，生成第一随机函数，其中写命令用于指示控制器将数据写入闪存 记忆; 并且逐位地调整数据的多个比特以产生伪随机比特序列，并将伪随机比特序列写入闪速存储器以表示数据，从而调整数据的数据模式分布。 还提供了一种相关联的存储器件及其控制器，其中控制器包括：ROM，被布置为存储程序代码; 布置成执行程序代码以控制对闪存的访问并管理多个块的微处理器; 以及布置成生成随机函数的随机发生器。 控制器可以执行数据模式管理。

公开(公告)号：US08423819B2

公开(公告)日：2013-04-16

申请号：US12717220

申请日：2010-03-04

Applicant: Kuo-Liang Yeh ,  Ken-Fu Hsu

Inventor： Kuo-Liang Yeh ,  Ken-Fu Hsu

IPC: G06F11/26

CPC classification number: G11C29/76 ,  G06F11/1666 ,  G11C29/883

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses.

Abstract translation: 本发明提供一种数据存储装置。 在一个实施例中，数据存储设备耦合到主机，并且包括降级存储器和控制器。 降级存储器包括多个块，其中每个块包括多个页面，每个页面包括多个扇区，并且一些扇区是缺陷扇区。 控制器产生用于在块中记录缺陷扇区的多个缺陷地址的缺陷表，从主机接收要写入降级存储器的多个数据扇区，确定用于存储数据的多个第一物理扇区地址 根据缺陷表发送写入命令到降级存储器，以指示降级存储器根据第一物理扇区地址将数据扇区写入降级存储器。

公开(公告)号：US20110107141A1

公开(公告)日：2011-05-05

申请号：US12717220

申请日：2010-03-04

Applicant: Kuo-Liang Yeh ,  Ken-Fu Hsu

Inventor： Kuo-Liang Yeh ,  Ken-Fu Hsu

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/02 ,  G06F11/20

CPC classification number: G11C29/76 ,  G06F11/1666 ,  G11C29/883

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses.

Abstract translation: 本发明提供一种数据存储装置。 在一个实施例中，数据存储设备耦合到主机，并且包括降级存储器和控制器。 降级存储器包括多个块，其中每个块包括多个页面，每个页面包括多个扇区，并且一些扇区是缺陷扇区。 控制器产生用于在块中记录缺陷扇区的多个缺陷地址的缺陷表，从主机接收要写入降级存储器的多个数据扇区，确定用于存储数据的多个第一物理扇区地址 根据缺陷表发送写入命令到降级存储器，以指示降级存储器根据第一物理扇区地址将数据扇区写入降级存储器。

公开(公告)号：US20110022997A1

公开(公告)日：2011-01-27

申请号：US12509496

申请日：2009-07-27

Applicant: Kuo-Liang Yeh

Inventor： Kuo-Liang Yeh

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H01L21/823456 ,  H01L27/0207

Abstract: A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error.

Abstract translation: 公开了一种用于推测门的有效尺寸，即有效宽度或有效长度的方法。 首先，提供包括第一栅极设计宽度和第一栅极设计长度的第一设计栅极组。 其次，通过计算分别获得第一设计栅极的固有栅极沟道电容和边缘电容。 然后借助于本征栅极沟道电容和边缘电容来预测尺寸误差，即宽度误差或长度误差，以计算计算出的反转电容和预测尺寸偏差。 之后，重复地预测尺寸误差以最小化预测的尺寸偏差并优化尺寸误差以获得优化的尺寸误差。 之后，通过优化的尺寸误差推测门的有效尺寸。

公开(公告)号：US20090184316A1

公开(公告)日：2009-07-23

申请号：US12016197

申请日：2008-01-17

Applicant: Yu-Hao Hsu ,  Kuo-Liang Yeh

Inventor： Yu-Hao Hsu ,  Kuo-Liang Yeh

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/14

Abstract: A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.

Abstract translation: 公开了一种提取栅极到源极/漏极和重叠电容的方法。 测量具有参考结构的第一测试键和具有新颖结构的第二测试键的第二电容的第一电容。 第二测试键可以至少包括形成在绝缘结构上的栅极，至少形成在绝缘结构上的触点和形成在触点上的金属层。 第二测试键的另一实施例可以包括至少形成在半导体衬底上的栅极，形成在其上的触点和形成在触点上的金属层。 又一实施例使用包括至少细长栅极和细长掺杂区域的测试键，并且在细长掺杂区域的端部上仅形成一个或几个触点。

公开(公告)号：US20120197593A1

公开(公告)日：2012-08-02

申请号：US13137190

申请日：2011-07-27

Applicant: Jyh-Chyurn Guo ,  Kuo-Liang Yeh

Inventor： Jyh-Chyurn Guo ,  Kuo-Liang Yeh

IPC: G01B7/02 ,  G06F15/00

CPC classification number: H01L22/30 ,  G01R31/2648 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capacitance per unit area.

Abstract translation: 半导体器件的参数提取方法包括：提供第一多指器件和第二多指器件，其中第一和第二多指器件之间的栅极指数不同; 执行开放式去嵌入，然后测量第一多指器件的第一固有栅极电容和第二多指器件的第二本征栅极电容的高频测试器件; 根据第一和第二固有栅极电容以及第一和第二栅极指数计算斜率; 执行用于计算多指端边缘电容的3D电容模拟; 利用长通道器件测量栅极电容并提取固有栅极电容，然后计算每单位面积的反向沟道电容; 以及根据斜率，多指端边缘电容和每单位面积的反向沟道电容计算半导体器件的δ沟道宽度。

公开(公告)号：US08146038B2

公开(公告)日：2012-03-27

申请号：US12509496

申请日：2009-07-27

Applicant: Kuo-Liang Yeh

Inventor： Kuo-Liang Yeh

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H01L21/823456 ,  H01L27/0207

Abstract: A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error.

Abstract translation: 公开了一种用于推测门的有效尺寸，即有效宽度或有效长度的方法。 首先，提供包括第一栅极设计宽度和第一栅极设计长度的第一设计栅极组。 其次，通过计算分别获得第一设计栅极的固有栅极沟道电容和边缘电容。 然后借助于本征栅极沟道电容和边缘电容来预测尺寸误差，即宽度误差或长度误差，以计算计算出的反转电容和预测尺寸偏差。 之后，重复地预测尺寸误差以最小化预测的尺寸偏差并优化尺寸误差以获得优化的尺寸误差。 之后，通过优化的尺寸误差推测门的有效尺寸。

公开(公告)号：US20060273705A1

公开(公告)日：2006-12-07

申请号：US11145920

申请日：2005-06-07

Applicant: Kuo-Liang Yeh

Inventor： Kuo-Liang Yeh

IPC: A47B88/00

CPC classification number: A47B88/493 ,  A47B2210/0032 ,  A47B2210/0059

Abstract: A drawer slide assembly includes an outer slide member securable to a side wall of a piece of furniture. An inner slide member with an inverted U-like shape is securable to a drawer and has two free ends bent inwards and a wave-like portion formed between the two free ends. An intermediate slide member is received in the inner member and defined with three raceways, wherein one raceway is defined between a lateral portion of the intermediate slide member and the wave-like portion, and the other two raceways are symmetrically defined at two opposite sides of the intermediate slide member. Three groups of rolling elements are respectively received in the raceways for slidingly coupling the inner slide member and the intermediate slide member. Axes of the rolling elements constitute a triangle. Whereby, the drawer slide assembly has good upright stability and low elastic deformation.

Abstract translation: 抽屉滑动组件包括可固定到一件家俱的侧壁的外滑动构件。 具有倒U字形状的内滑动构件可固定在抽屉上，并具有向内弯曲的两个自由端和形成在两个自由端之间的波浪状部分。 中间滑动构件被容纳在内部构件中并且被限定有三个滚道，其中一个滚道被限定在中间滑动构件的侧部和波浪形部分之间，而另外两个滚道对称地限定在 中间滑动构件。 三组滚动元件分别容纳在用于滑动地联接内部滑动构件和中间滑动构件的滚道中。 滚动元件的轴构成三角形。 由此，抽屉滑轨组件具有良好的直立稳定性和低弹性变形。

公开(公告)号：US08460766B2

公开(公告)日：2013-06-11

申请号：US13157657

申请日：2011-06-10

Applicant: Pei-Chen Huang ,  Kuo-Chang Wang ,  Kuo-Liang Yeh ,  An-Cheng Chen ,  Kung-Lung Cheng ,  Shyue-Ming Jang

Inventor： Pei-Chen Huang ,  Kuo-Chang Wang ,  Kuo-Liang Yeh ,  An-Cheng Chen ,  Kung-Lung Cheng ,  Shyue-Ming Jang

IPC: C09K19/30 ,  C09K19/12 ,  C09K19/20 ,  C07C22/08 ,  C07C25/13 ,  C07C25/24

CPC classification number: C09K19/46 ,  C09K19/3066 ,  C09K19/44 ,  C09K2019/0466 ,  C09K2019/123 ,  C09K2019/3004 ,  C09K2019/3009 ,  C09K2019/301 ,  C09K2019/3016 ,  C09K2019/3037 ,  C09K2019/3083 ,  Y10T428/10

Abstract: A liquid crystal compound of Formula (1) is provided below: wherein R is hydrogen, linear or branching C1-15 alkyl, linear or branching C1-15 alkyl (wherein any one of —CH2— is replaced by —O—, —S—, —CO—, —CO—O—, or —O—CO—), linear or branching C2-15 alkenyl, or linear or branching C2-15 alkenyl (wherein any one of —CH2— is replaced by —O—, —S—, —CO—, —CO—O—, or —O—CO—), A and B are, independently, cyclohexane, cyclohexane (wherein any one of —CH2— is replaced by —O— or —NH—), benzene, or benzene (wherein any one of —CH2═ is replaced by —N═), X is a single bond, —CO—O—, —O—CO—, —CH2O—, —OCH2—, —CH2CH2—, —C═C—, —C≡C—, —CF2O—, or —OCF2—, Q is oxygen or CH2, Y is CF3, CF2H, or CFH2, L1, L2, and L3 are, independently, hydrogen or fluorine, and m is 0, 1, or 2.

Abstract translation: 下面提供式（1）的液晶化合物：其中R是氢，直链或支链C1-15烷基，直链或支链C1-15烷基（其中-CH2-中的任一个被-O - ， - S - ， - CO-，-CO-O-或-O-CO-），直链或支链C2-15烯基，或直链或支链C2-15链烯基（其中-CH2-中的任一个被-O- ，-S-，-CO-，-CO-O-或-O-CO-），A和B独立地是环己烷，环己烷（其中-CH 2 - 中的任一个被-O-或-NH - ），苯或苯（其中-CH 2 =中的任何一个被-N =取代），X是单键，-CO-O-，-O-CO-，-CH 2 O-，-OCH 2 - CH 2 CH 2 - ， - C = C - ， - C = C - ， - CF 2 O-或-OCF 2 - ，Q为氧或CH 2，Y为CF 3，CF 2 H或CFH 2，L 1，L 2和L 3独立地为氢 或氟，m为0,1或2。