公开(公告)号：US08415672B2

公开(公告)日：2013-04-09

申请号：US13006580

申请日：2011-01-14

申请人： Chin-Wei Hu ,  Ching-Sang Chuang ,  Chia-Yu Chen

发明人： Chin-Wei Hu ,  Ching-Sang Chuang ,  Chia-Yu Chen

IPC分类号： H01L29/786

CPC分类号： H01L29/66757 ,  H01L29/78606

摘要： This invention provides a transistor with an etching stop layer and a manufacturing method thereof. The transistor structure includes a substrate, a crystalline semiconductor layer, an etching stop structure, an ohmic contact layer, a source, a drain, a gate insulating layer, and a gate. The manufacturing method is performed by patterning the ohmic contact layer and the crystalline semiconductor layer at the same time with the same mask; and patterning the ohmic contact layer and the source/drain layer at the same time with another the same mask.

摘要翻译： 本发明提供具有蚀刻停止层的晶体管及其制造方法。 晶体管结构包括衬底，晶体半导体层，蚀刻停止结构，欧姆接触层，源极，漏极，栅极绝缘层和栅极。 制造方法通过以相同的掩模同时对欧姆接触层和结晶半导体层进行图案化来进行; 并用同样的掩模同时对欧姆接触层和源极/漏极层进行构图。

公开(公告)号：US20120049195A1

公开(公告)日：2012-03-01

申请号：US13006580

申请日：2011-01-14

申请人： Chin-Wei Hu ,  Ching-Sang Chuang ,  Chia-Yu Chen

发明人： Chin-Wei Hu ,  Ching-Sang Chuang ,  Chia-Yu Chen

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66757 ,  H01L29/78606

摘要： This invention provides a transistor with an etching stop layer and a manufacturing method thereof. The transistor structure includes a substrate, a crystalline semiconductor layer, an etching stop structure, an ohmic contact layer, a source, a drain, a gate insulating layer, and a gate. The manufacturing method is performed by patterning the ohmic contact layer and the crystalline semiconductor layer at the same time with the same mask; and patterning the ohmic contact layer and the source/drain layer at the same time with another the same mask.

摘要翻译： 本发明提供具有蚀刻停止层的晶体管及其制造方法。 晶体管结构包括衬底，晶体半导体层，蚀刻停止结构，欧姆接触层，源极，漏极，栅极绝缘层和栅极。 制造方法通过以相同的掩模同时对欧姆接触层和结晶半导体层进行图案化来进行; 并用同样的掩模同时对欧姆接触层和源极/漏极层进行构图。

公开(公告)号：US07417279B2

公开(公告)日：2008-08-26

申请号：US11205108

申请日：2005-08-17

申请人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

发明人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

IPC分类号： H01L29/94

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1203

摘要： An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.

摘要翻译： EEPROM包括基板，形成在基板上的第一半导体层和第二半导体层。 第一半导体层通过沟槽与第二半导体层隔离。 第一源极和第一漏极位于第一半导体层的相对两侧。 在第一半导体层上形成第一电介质层，在第一电介质层上形成第一浮栅。 第二源极和第二漏极位于第二半导体层的两个相对侧。 在第二半导体层上形成第二电介质层，在第二电介质层上形成第二浮栅。 第一浮栅和第二浮栅电连接。

公开(公告)号：US20100012944A1

公开(公告)日：2010-01-21

申请号：US12400768

申请日：2009-03-09

申请人： An-Thung Cho ,  Chin-Wei Hu ,  Ming-Wei Sun ,  Chih-Wei Chao ,  Chia-Tien Peng ,  Kun-Chih Lin

发明人： An-Thung Cho ,  Chin-Wei Hu ,  Ming-Wei Sun ,  Chih-Wei Chao ,  Chia-Tien Peng ,  Kun-Chih Lin

IPC分类号： H01L29/04 ,  H01L21/84

CPC分类号： H01L29/78633 ,  H01L29/78675

摘要： A thin film transistor (TFT) formed on a transparent substrate is provided. The thin film transistor includes a patterned semiconductor layer, a gate insulating layer disposed on the patterned semiconductor layer, a gate electrode disposed on the gate insulating layer, and a patterned light-absorbing layer. The patterned semiconductor layer includes a channel region, and a source region and a drain region disposed on two opposite sides of the channel region in the pattern semiconductor layer. The patterned light-absorbing layer is disposed between the transparent substrate and the patterned semiconductor layer.

摘要翻译： 提供了形成在透明基板上的薄膜晶体管（TFT）。 薄膜晶体管包括图案化半导体层，设置在图案化半导体层上的栅极绝缘层，设置在栅极绝缘层上的栅电极和图案化的光吸收层。 图案化的半导体层包括沟道区，以及设置在图案半导体层中的沟道区的两个相对侧上的源极区和漏极区。 图案化的光吸收层设置在透明基板和图案化的半导体层之间。

公开(公告)号：US20090117698A1

公开(公告)日：2009-05-07

申请号：US12180521

申请日：2008-07-26

申请人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

发明人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1203

摘要： An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.

摘要翻译： EEPROM包括基板，形成在基板上的第一半导体层和第二半导体层。 第一半导体层通过沟槽与第二半导体层隔离。 第一源极和第一漏极位于第一半导体层的相对两侧。 在第一半导体层上形成第一电介质层，在第一电介质层上形成第一浮栅。 第二源极和第二漏极位于第二半导体层的两个相对侧。 在第二半导体层上形成第二电介质层，在第二电介质层上形成第二浮栅。 第一浮栅和第二浮栅电连接。

公开(公告)号：US20100006847A1

公开(公告)日：2010-01-14

申请号：US12241071

申请日：2008-09-30

申请人： Chin-Wei Hu ,  Kun-Chih Lin

发明人： Chin-Wei Hu ,  Kun-Chih Lin

IPC分类号： H01L21/8238 ,  H01L29/786

CPC分类号： H01L27/1288 ,  H01L21/2652 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621

摘要： A semiconductor device and the method for fabricating the same are disclosed. The fabrication method includes forming a PMOS device and an NMOS device on a substrate, wherein the PMOS device includes a first poly-silicon island, a gate dielectric layer covering the first poly-silicon island, and a first gate on the gate dielectric layer. The method of fabrication the PMOS device includes performing a P-type ion implantation process on the first poly-silicon island to form a plurality of P-type heavily doped regions and a plurality of P-type lightly doped regions. The length of the channel region is substantially less than 3 micron, and the length of at least one of the P-type lightly doped regions substantially is 10%-80% of the length of the channel region. The P-type lightly doped regions are used to improve the short channel effect of the PMOS device.

摘要翻译： 公开了一种半导体器件及其制造方法。 该制造方法包括在衬底上形成PMOS器件和NMOS器件，其中PMOS器件包括第一多晶硅岛，覆盖第一多晶硅岛的栅极电介质层和栅极介电层上的第一栅极。 制造PMOS器件的方法包括在第一多晶硅岛上执行P型离子注入工艺以形成多个P型重掺杂区域和多个P型轻掺杂区域。 沟道区的长度基本上小于3微米，并且P型轻掺杂区中的至少一个的长度基本上是沟道区长度的10％-80％。 P型轻掺杂区域用于改善PMOS器件的短沟道效应。

公开(公告)号：US07572700B2

公开(公告)日：2009-08-11

申请号：US12180521

申请日：2008-07-26

申请人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

发明人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1203

摘要： An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.

摘要翻译： EEPROM包括基板，形成在基板上的第一半导体层和第二半导体层。 第一半导体层通过沟槽与第二半导体层隔离。 第一源极和第一漏极位于第一半导体层的相对两侧。 在第一半导体层上形成第一电介质层，在第一电介质层上形成第一浮栅。 第二源极和第二漏极位于第二半导体层的两个相对侧。 在第二半导体层上形成第二电介质层，在第二电介质层上形成第二浮栅。 第一浮栅和第二浮栅电连接。

公开(公告)号：US20060237765A1

公开(公告)日：2006-10-26

申请号：US11205108

申请日：2005-08-17

申请人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

发明人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

IPC分类号： H01L29/76

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1203

摘要： An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.

公开(公告)号：US06737294B1

公开(公告)日：2004-05-18

申请号：US10463677

申请日：2003-06-18

申请人： Chin-Wei Hu ,  Kun-Hong Chen

发明人： Chin-Wei Hu ,  Kun-Hong Chen

IPC分类号： H01L2100

CPC分类号： H01L27/1248 ,  H01L27/1214

摘要： A plurality of thin-film transistors are formed on a substrate. An insulating layer and a metal layer are formed on the substrate, the metal layer including a source electrode and a drain electrode connecting to each of the transistors, and a channel region defined between the source electrode and the drain electrode. An organic layer is formed to cover the metal layer and the insulating layer. A transparent conductive layer is formed on the organic layer. Therein the insulating layer is simultaneously solidified when forming the organic layer, thus reducing surface leakage currents of the substrate.

摘要翻译： 在基板上形成多个薄膜晶体管。 绝缘层和金属层形成在基板上，金属层包括连接到每个晶体管的源电极和漏电极以及限定在源电极和漏电极之间的沟道区。 形成有机层以覆盖金属层和绝缘层。 在有机层上形成透明导电层。 其中，当形成有机层时，绝缘层同时固化，从而减小衬底的表面泄漏电流。