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公开(公告)号：US08724406B2
公开(公告)日：2014-05-13
申请号：US13524070
申请日：2012-06-15
IPC分类号： G11C7/00
CPC分类号： G09G3/3677 , G09G2310/0286
摘要： A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.
摘要翻译： 双向移位寄存器包括第一寄存器电路和第二寄存器电路。 第一寄存器电路包括第一寄存器级和具有n个扫描信号输出端的第一输出缓冲级。 第一寄存器级电耦合到第三电压源。 第一输出缓冲级电耦合到第二电压源和第一电压源。 第二寄存器电路具有与第一寄存器电路相似的电路结构; 其中第一寄存器电路和第二寄存器电路各使用n + 1个时钟信号线，并且n是正整数。
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公开(公告)号：US20130173870A1
公开(公告)日：2013-07-04
申请号：US13524070
申请日：2012-06-15
IPC分类号： G06F12/00
CPC分类号： G09G3/3677 , G09G2310/0286
摘要： A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.
摘要翻译： 双向移位寄存器包括第一寄存器电路和第二寄存器电路。 第一寄存器电路包括第一寄存器级和具有n个扫描信号输出端的第一输出缓冲级。 第一寄存器级电耦合到第三电压源。 第一输出缓冲级电耦合到第二电压源和第一电压源。 第二寄存器电路具有与第一寄存器电路相似的电路结构; 其中第一寄存器电路和第二寄存器电路各使用n + 1个时钟信号线，并且n是正整数。
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公开(公告)号：US08860651B2
公开(公告)日：2014-10-14
申请号：US13458465
申请日：2012-04-27
IPC分类号： G09G3/36
CPC分类号： G11C19/28 , G09G3/3674 , G09G2310/0286 , G09G2330/021
摘要： A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.
摘要翻译： 门驱动器包括级联连接的驱动级。 每个驱动级包括第一移位寄存器电路和第二移位寄存器电路。 第一移位寄存器电路被配置为输出当前级驱动信号和下一级驱动信号。 第二移位寄存器电路电耦合到第一移位寄存器电路，并被配置为输出当前级门信号，第一下级门信号和第二下级门信号。 此外，还提供了显示面板。
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公开(公告)号：US20130135284A1
公开(公告)日：2013-05-30
申请号：US13458465
申请日：2012-04-27
IPC分类号： G09G5/00
CPC分类号： G11C19/28 , G09G3/3674 , G09G2310/0286 , G09G2330/021
摘要： A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.
摘要翻译： 门驱动器包括级联连接的驱动级。 每个驱动级包括第一移位寄存器电路和第二移位寄存器电路。 第一移位寄存器电路被配置为输出当前级驱动信号和下一级驱动信号。 第二移位寄存器电路电耦合到第一移位寄存器电路，并被配置为输出当前级门信号，第一下级门信号和第二下级门信号。 此外，还提供了显示面板。
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5.发明授权公开(公告)号：US09129574B2
公开(公告)日：2015-09-08
申请号：US13441940
申请日：2012-04-09
CPC分类号： G09G3/3696 , G09G3/3659 , G09G3/3674 , G09G2300/0871 , G09G2310/0218 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N−1)th shift register stage for generating an (N−1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N−1)th gate signal and the second clock.
摘要翻译： 栅极驱动电路包括设置在像素阵列的不同侧的移位寄存器电路和辅助电路。 移位寄存器电路包括用于根据第一时钟产生第（N-1）门信号的第（N-1）移位寄存器级，用于根据第二时钟产生第N门信号的第N移位寄存器级，以及 用于根据第三时钟产生第（N + 1）门信号的第（N + 1）移位寄存器级。 辅助电路包括第一晶体管。 第一晶体管根据第（N-1）栅极信号和第二时钟在第N栅极信号上执行信号电压稳定和电平切换加速操作。
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公开(公告)号：US08259895B2
公开(公告)日：2012-09-04
申请号：US13330489
申请日：2011-12-19
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
摘要翻译： 双向移位寄存器包括用于分别提供第一，第二，第三和第四控制信号Bi1，Bi2，Bi3和Bi4的第一，第二，第三和第四控制信号总线，以及分别电连接的多个移位寄存器级， 每个移位寄存器级具有第一和第二输入节点，其中移位寄存器级被分组为第一部分和第二部分，其中第一部分中每个移位寄存器级的第一和第二输入节点电耦合到第一部分和第二部分， 分别用于接收第一和第二控制信号Bi1和Bi2的第二控制信号总线和第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制信号总线， 第三和第四控制信号Bi3和Bi4。
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7.发明授权Gate driver stage outputting multiple, partially overlapping gate-line signals to a liquid crystal display 有权栅极驱动器级将多个部分重叠的栅极线信号输出到液晶显示器公开(公告)号：US09030399B2
公开(公告)日：2015-05-12
申请号：US13403434
申请日：2012-02-23
CPC分类号： G09G3/20 , G09G3/3677 , G09G2310/0218 , G09G2310/0286
摘要： A gate driver for driving a TFT-LCD panel includes a number of gate-driver circuits arranged in groups and stages. Each gate-driver circuit has a main driver and an output section. The main driver is used to provide a charging signal to the output section which has two or more output circuits. Each of the output circuits is configured to provide a gate-line signal in response to the charging signal and a clock signal. The gate-driver circuit uses fewer switching elements, such as thin-film transistors, than the conventional circuit. When the gate driver is integrated in a TFT-LCD display panel and disposed within the periphery area around the display area, it is desirable to reduce or minimize the number of switching elements in the gate driver so that the periphery area can be reduced.
摘要翻译： 用于驱动TFT-LCD面板的栅极驱动器包括以组和阶段布置的多个栅极驱动器电路。 每个栅极驱动器电路具有主驱动器和输出部分。 主驱动器用于向具有两个或更多个输出电路的输出部分提供充电信号。 每个输出电路被配置为响应于充电信号和时钟信号提供栅极线信号。 栅极驱动器电路比常规电路使用更少的开关元件，例如薄膜晶体管。 当栅极驱动器集成在TFT-LCD显示面板中并且设置在显示区域周围的周边区域中时，期望减小或最小化栅极驱动器中的开关元件的数量，使得可以减小外围区域。
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公开(公告)号：US08102962B2
公开(公告)日：2012-01-24
申请号：US12685294
申请日：2010-01-11
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
摘要翻译： 双向移位寄存器包括分别提供第一，第二，第三和第四控制信号Bi1，Bi2，Bi3和Bi4的第一，第二，第三和第四控制信号总线，以及分别电连接的多个移位寄存器级， 每个移位寄存器级具有第一输入节点和第二输入节点，其中多个移位寄存器级被分组为第一部分和第二部分，其中第一部分中每个移位寄存器级的第一和第二输入节点是 电耦合到第一和第二控制信号总线以分别接收第一和第二控制信号Bi1和Bi2，并且第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制器 用于分别接收第三和第四控制信号Bi3和Bi4的信号总线。
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公开(公告)号：US20130127797A1
公开(公告)日：2013-05-23
申请号：US13441940
申请日：2012-04-09
IPC分类号： G09G5/00
CPC分类号： G09G3/3696 , G09G3/3659 , G09G3/3674 , G09G2300/0871 , G09G2310/0218 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N−1)th shift register stage for generating an (N−1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N−1)th gate signal and the second clock.
摘要翻译： 栅极驱动电路包括设置在像素阵列的不同侧的移位寄存器电路和辅助电路。 移位寄存器电路包括用于根据第一时钟产生第（N-1）门信号的第（N-1）移位寄存器级，用于根据第二时钟产生第N门信号的第N移位寄存器级，以及 用于根据第三时钟产生第（N + 1）门信号的第（N + 1）移位寄存器级。 辅助电路包括第一晶体管。 第一晶体管根据第（N-1）栅极信号和第二时钟在第N栅极信号上执行信号电压稳定和电平切换加速操作。
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公开(公告)号：US20120087461A1
公开(公告)日：2012-04-12
申请号：US13330489
申请日：2011-12-19
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
摘要翻译： 双向移位寄存器包括用于分别提供第一，第二，第三和第四控制信号Bi1，Bi2，Bi3和Bi4的第一，第二，第三和第四控制信号总线，以及分别电连接的多个移位寄存器级， 每个移位寄存器级具有第一和第二输入节点，其中移位寄存器级被分组为第一部分和第二部分，其中第一部分中每个移位寄存器级的第一和第二输入节点电耦合到第一部分和第二部分， 分别用于接收第一和第二控制信号Bi1和Bi2的第二控制信号总线和第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制信号总线， 第三和第四控制信号Bi3和Bi4。
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