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公开(公告)号：US20130222357A1
公开(公告)日：2013-08-29
申请号：US13403434
申请日：2012-02-23
CPC分类号： G09G3/20 , G09G3/3677 , G09G2310/0218 , G09G2310/0286
摘要： A gate driver for driving a TFT-LCD panel includes a number of gate-driver circuits arranged in groups and stages. Each gate-driver circuit has a main driver and an output section. The main driver is used to provide a charging signal to the output section which has two or more output circuits. Each of the output circuits is configured to provide a gate-line signal in response to the charging signal and a clock signal. The gate-driver circuit uses fewer switching elements, such as thin-film transistors, than the conventional circuit. When the gate driver is integrated in a TFT-LCD display panel and disposed within the periphery area around the display area, it is desirable to reduce or minimize the number of switching elements in the gate driver so that the periphery area can be reduced.
摘要翻译： 用于驱动TFT-LCD面板的栅极驱动器包括以组和阶段布置的多个栅极驱动器电路。 每个栅极驱动器电路具有主驱动器和输出部分。 主驱动器用于向具有两个或更多个输出电路的输出部分提供充电信号。 每个输出电路被配置为响应于充电信号和时钟信号提供栅极线信号。 栅极驱动器电路比常规电路使用更少的开关元件，例如薄膜晶体管。 当栅极驱动器集成在TFT-LCD显示面板中并且设置在显示区域周围的周边区域中时，期望减小或最小化栅极驱动器中的开关元件的数量，使得可以减小外围区域。
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公开(公告)号：US08405787B2
公开(公告)日：2013-03-26
申请号：US12405247
申请日：2009-03-17
IPC分类号： G02F1/1343
CPC分类号： H01L27/1255 , G02F1/136286 , H01L27/1214
摘要： A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors.
摘要翻译： 三栅极像素结构包括三个子像素区域，三个栅极线，数据线，三个薄膜晶体管（TFT），三个像素电极和公共线。 栅极线沿着第一方向设置，并且数据线沿着第二方向设置。 TFT分别设置在子像素区域中，其中每个TFT具有电连接到相应的栅极线的栅电极，与数据线电连接的源电极和漏电极。 三个像素电极分别设置在三个子像素区域中，并且每个像素电极分别电连接到一个TFT的漏电极。 公共线与栅极线交叉并且部分地重叠三条栅极线，并且公共线和三个像素电极部分地重叠以分别形成三个存储电容器。
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3.发明授权Bidirectional controlling device for increasing resistance of elements on voltage stress 有权双向控制设备，用于对电压应力增大元件的电阻公开(公告)号：US07852976B2
公开(公告)日：2010-12-14
申请号：US12135220
申请日：2008-06-09
申请人： Chen-Ming Chen , Kuang-Hsiang Liu , Sheng-Chao Liu
发明人： Chen-Ming Chen , Kuang-Hsiang Liu , Sheng-Chao Liu
IPC分类号： G11C19/00
CPC分类号： H03K17/687 , H03K17/002
摘要： A bidirectional controlling device is utilized for receiving two input signals, which are respectively provided from a first input terminal and a second input terminal, and for respectively providing two output signals to a first output terminal and a second output terminal, by controlling a plurality of switch sets.
摘要翻译： 双向控制装置用于接收两个输入信号，其分别从第一输入端子和第二输入端子提供，并用于分别提供两个输出信号给第一输出端和第二输出端，通过控制多个 切换台。
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4.发明授权Gate driver stage outputting multiple, partially overlapping gate-line signals to a liquid crystal display 有权栅极驱动器级将多个部分重叠的栅极线信号输出到液晶显示器公开(公告)号：US09030399B2
公开(公告)日：2015-05-12
申请号：US13403434
申请日：2012-02-23
CPC分类号： G09G3/20 , G09G3/3677 , G09G2310/0218 , G09G2310/0286
摘要： A gate driver for driving a TFT-LCD panel includes a number of gate-driver circuits arranged in groups and stages. Each gate-driver circuit has a main driver and an output section. The main driver is used to provide a charging signal to the output section which has two or more output circuits. Each of the output circuits is configured to provide a gate-line signal in response to the charging signal and a clock signal. The gate-driver circuit uses fewer switching elements, such as thin-film transistors, than the conventional circuit. When the gate driver is integrated in a TFT-LCD display panel and disposed within the periphery area around the display area, it is desirable to reduce or minimize the number of switching elements in the gate driver so that the periphery area can be reduced.
摘要翻译： 用于驱动TFT-LCD面板的栅极驱动器包括以组和阶段布置的多个栅极驱动器电路。 每个栅极驱动器电路具有主驱动器和输出部分。 主驱动器用于向具有两个或更多个输出电路的输出部分提供充电信号。 每个输出电路被配置为响应于充电信号和时钟信号提供栅极线信号。 栅极驱动器电路比常规电路使用更少的开关元件，例如薄膜晶体管。 当栅极驱动器集成在TFT-LCD显示面板中并且设置在显示区域周围的周边区域中时，期望减小或最小化栅极驱动器中的开关元件的数量，使得可以减小外围区域。
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公开(公告)号：US20130135284A1
公开(公告)日：2013-05-30
申请号：US13458465
申请日：2012-04-27
IPC分类号： G09G5/00
CPC分类号： G11C19/28 , G09G3/3674 , G09G2310/0286 , G09G2330/021
摘要： A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.
摘要翻译： 门驱动器包括级联连接的驱动级。 每个驱动级包括第一移位寄存器电路和第二移位寄存器电路。 第一移位寄存器电路被配置为输出当前级驱动信号和下一级驱动信号。 第二移位寄存器电路电耦合到第一移位寄存器电路，并被配置为输出当前级门信号，第一下级门信号和第二下级门信号。 此外，还提供了显示面板。
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6.发明授权Gate driving circuit having a shift register stage capable of pulling down gate signals of a plurality of shift register stages 有权门驱动电路具有能够拉低多个移位寄存器级的门信号的移位寄存器级公开(公告)号：US08411074B2
公开(公告)日：2013-04-02
申请号：US12488581
申请日：2009-06-21
申请人： Sheng-Chao Liu , Kuang-Hsiang Liu
发明人： Sheng-Chao Liu , Kuang-Hsiang Liu
CPC分类号： G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G09G2310/0291
摘要： A high-reliability gate driving circuit includes a plurality of odd shift register stages and a plurality of even shift register stages. Each odd shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock, and further functions to pull down a gate signal of at least one even gate line or at least one odd gate line different from the corresponding odd gate line. Each even shift register stage generates a corresponding gate signal furnished to a corresponding even gate line according to a third clock and a fourth clock having a phase opposite to the third clock, and further functions to pull down a gate signal of at least one odd gate line or at least one even gate line different from the corresponding even gate line.
摘要翻译： 高可靠性门驱动电路包括多个奇数移位寄存器级和多个偶移位寄存器级。 每个奇数移位寄存器级产生根据第一时钟提供给相应奇数栅极线的相应门信号和具有与第一时钟相反的相位的第二时钟，并且还用于下拉至少一个偶数栅极的栅极信号 线或至少一个与相应的奇数行线不同的奇数行线。 每个偶移位寄存器级产生根据第三时钟提供给对应偶极线的相应门信号，以及具有与第三时钟相反的相位的第四时钟，并且还用于下拉至少一个奇数门的门信号 线或至少一个与相应的偶数栅极线不同的偶数栅极线。
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公开(公告)号：US08102962B2
公开(公告)日：2012-01-24
申请号：US12685294
申请日：2010-01-11
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
摘要翻译： 双向移位寄存器包括分别提供第一，第二，第三和第四控制信号Bi1，Bi2，Bi3和Bi4的第一，第二，第三和第四控制信号总线，以及分别电连接的多个移位寄存器级， 每个移位寄存器级具有第一输入节点和第二输入节点，其中多个移位寄存器级被分组为第一部分和第二部分，其中第一部分中每个移位寄存器级的第一和第二输入节点是 电耦合到第一和第二控制信号总线以分别接收第一和第二控制信号Bi1和Bi2，并且第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制器 用于分别接收第三和第四控制信号Bi3和Bi4的信号总线。
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公开(公告)号：US20110080384A1
公开(公告)日：2011-04-07
申请号：US12895922
申请日：2010-10-01
申请人： Sheng-Chao Liu , Kuang-Hsiang Liu
发明人： Sheng-Chao Liu , Kuang-Hsiang Liu
CPC分类号： G09G3/20 , G02F1/13452 , G02F1/167 , G02F2201/50 , G09G2300/0417 , G09G2300/0426 , G09G2330/04 , H01L27/0296 , H01L27/12 , H01L27/1248
摘要： A flat panel display with a circuit protection structure is provided. The flat panel display includes a substrate, an electrode array control circuit, a driving circuit, a display panel, and a protection unit. The substrate has a first surface. The electrode array control circuit is formed on the first surface. The driving circuit is formed on the first surface and on one side of the electrode array control circuit. The display panel including a plurality of display particles is disposed on the electrode array control circuit. The electrode array control circuit controls operations of the display particles. The protection unit is formed on one side of the display panel to cover the driving circuit.
摘要翻译： 提供具有电路保护结构的平板显示器。 平板显示器包括基板，电极阵列控制电路，驱动电路，显示面板和保护单元。 衬底具有第一表面。 电极阵列控制电路形成在第一表面上。 驱动电路形成在电极阵列控制电路的第一表面和一侧上。 包括多个显示颗粒的显示面板设置在电极阵列控制电路上。 电极阵列控制电路控制显示颗粒的操作。 保护单元形成在显示面板的一侧以覆盖驱动电路。
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公开(公告)号：US20100238143A1
公开(公告)日：2010-09-23
申请号：US12488581
申请日：2009-06-21
申请人： Sheng-Chao Liu , Kuang-Hsiang Liu
发明人： Sheng-Chao Liu , Kuang-Hsiang Liu
IPC分类号： G09G5/00
CPC分类号： G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G09G2310/0291
摘要： A high-reliability gate driving circuit includes a plurality of odd shift register stages and a plurality of even shift register stages. Each odd shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock, and further functions to pull down a gate signal of at least one even gate line or at least one odd gate line different from the corresponding odd gate line. Each even shift register stage generates a corresponding gate signal furnished to a corresponding even gate line according to a third clock and a fourth clock having a phase opposite to the third clock, and further functions to pull down a gate signal of at least one odd gate line or at least one even gate line different from the corresponding even gate line.
摘要翻译： 高可靠性门驱动电路包括多个奇数移位寄存器级和多个偶移位寄存器级。 每个奇数移位寄存器级产生根据第一时钟提供给相应奇数栅极线的相应门信号和具有与第一时钟相反的相位的第二时钟，并且还用于下拉至少一个偶数栅极的栅极信号 线或至少一个与相应的奇数行线不同的奇数行线。 每个偶移位寄存器级产生根据第三时钟提供给对应偶极线的相应门信号，以及具有与第三时钟相反的相位的第四时钟，并且还用于下拉至少一个奇数门的门信号 线或至少一个与相应的偶数栅极线不同的偶数栅极线。
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公开(公告)号：US20100067646A1
公开(公告)日：2010-03-18
申请号：US12212143
申请日：2008-09-17
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3677
摘要： A shift register comprises a plurality of stages, {Sj}, j=1, 2, . . . , N, N being a positive integer. Each stage Sj includes a first input, IN1, a second input, IN2, a third input, IN3, a fourth input, IN4, a fifth input, IN5 and a sixth input, IN6; an output, OUT; a first transistor M1 having a gate electrically coupled to the third input IN3, a drain electrically coupled to the first input IN1, and a source electrically coupled to a node N1, respectively; a second transistor M2 having a gate electrically coupled to the fourth input IN4, a drain electrically coupled to the node N1, and a source electrically coupled to the second input IN2, respectively; a third transistor M3 having a gate electrically coupled to a node N2 that is electrically coupled to the node N1, a drain electrically coupled to the fifth input IN5, and a source electrically coupled to the output OUT, respectively; and a fourth transistor M4 having a gate electrically coupled to a node N3, a drain electrically coupled to the output OUT, and a source electrically coupled to the sixth input IN6, respectively.
摘要翻译： 移位寄存器包括多个级，{Sj}，j = 1,2，...。 。 。 ，N，N为正整数。 每个级Sj包括第一输入IN1，第二输入IN2，第三输入IN3，第四输入IN4，第五输入IN5和第六输入IN6; 输出，OUT; 第一晶体管M1，其具有电耦合到第三输入IN3的栅极，电耦合到第一输入IN1的漏极和分别电耦合到节点N1的源极; 具有电耦合到第四输入IN4的栅极的第二晶体管M2，电耦合到节点N1的漏极和分别电耦合到第二输入IN2的源极; 第三晶体管M3，其具有电耦合到节点N2的栅极电耦合到节点N1，电耦合到第五输入IN5的漏极和分别电耦合到输出OUT的源极; 以及第四晶体管M4，其具有电耦合到节点N3的栅极，电耦合到输出OUT的漏极和分别电耦合到第六输入IN6的源极。
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