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公开(公告)号：US20090174039A1
公开(公告)日：2009-07-09
申请号：US12318774
申请日：2009-01-08
Applicant: Chan-Mi Lee , Jong-Chul Park
Inventor： Chan-Mi Lee , Jong-Chul Park
IPC: H01L27/00
CPC classification number: H01L29/66553 , H01L29/42376 , H01L29/66621
Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface.
Abstract translation: 提供半导体器件及其形成方法。 半导体器件可以包括半导体衬底，该半导体衬底包括主表面，该主表面被配置为限定从主表面的给定区域向下并且朝向主表面开口的凹槽，沟槽和空腔。
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2.发明授权Methods of forming a conductive layer structure and methods of manufacturing a recessed channel transistor including the same 失效形成导电层结构的方法以及制造包括该沟道晶体管的凹陷沟道晶体管的方法公开(公告)号：US08067285B2
公开(公告)日：2011-11-29
申请号：US12968711
申请日：2010-12-15
Applicant: Jong-Chul Park , Chan-Mi Lee , Sang-Sup Jeong
Inventor： Jong-Chul Park , Chan-Mi Lee , Sang-Sup Jeong
IPC: H01L21/336 , H01L29/66
CPC classification number: H01L29/4236 , H01L27/10876 , H01L27/10894 , H01L27/11 , H01L27/1104 , H01L29/66621
Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.
Abstract translation: 在形成导电层结构的方法和制造凹槽沟道晶体管的方法中，第一绝缘层和第一导电层依次形成在具有第一区域的第二区域的基板上， 形成区域在第一区域。 通过蚀刻衬底的暴露区域，在凹部形成区域中形成凹部。 第二绝缘层共形地形成在凹槽的侧壁和底部上。 在第二绝缘层上形成第二导电层图案以填充凹部的一部分。 在第二导电层图案和凹部的侧壁上的第二绝缘层上形成间隔物。 在第二导电层图案和间隔物上形成第三导电层图案以填充凹部。
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Patent Agency Ranking
3.发明申请公开(公告)号：US20110151633A1
公开(公告)日：2011-06-23
申请号：US12968711
申请日：2010-12-15
Applicant: Jong-Chul PARK , Chan-Mi Lee , Sang-Sup Jeong
Inventor： Jong-Chul PARK , Chan-Mi Lee , Sang-Sup Jeong
IPC: H01L21/28
CPC classification number: H01L29/4236 , H01L27/10876 , H01L27/10894 , H01L27/11 , H01L27/1104 , H01L29/66621
Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.
Abstract translation: 在形成导电层结构的方法和制造凹槽沟道晶体管的方法中，第一绝缘层和第一导电层依次形成在具有第一区域的第二区域的基板上， 形成区域在第一区域。 通过蚀刻衬底的暴露区域，在凹部形成区域中形成凹部。 第二绝缘层共形地形成在凹槽的侧壁和底部上。 在第二绝缘层上形成第二导电层图案以填充凹部的一部分。 在第二导电层图案和凹部的侧壁上的第二绝缘层上形成间隔物。 在第二导电层图案和间隔物上形成第三导电层图案以填充凹部。
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公开(公告)号：US20120055908A1
公开(公告)日：2012-03-08
申请号：US13220084
申请日：2011-08-29
Applicant: Sang-Wuk Park , Geum-Jung Seong , Kye-Hyun Baek , Yong-Jin Kim , Chan-Mi Lee
Inventor： Sang-Wuk Park , Geum-Jung Seong , Kye-Hyun Baek , Yong-Jin Kim , Chan-Mi Lee
CPC classification number: B23K26/0661 , B23K26/032 , B23K26/361 , H01J37/32972 , H01L22/12 , H01L22/26
Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.
Abstract translation: 提供了蚀刻系统和控制蚀刻工艺条件的方法。 蚀刻系统包括将入射光照射到目标晶片中的光源，光强度测量单元，其根据由来自目标晶片的反射光之间的干涉产生的干涉光的波长来测量光强度;信号处理器，其检测 当干扰光的强度根据波长变化时产生强度极值的时间点，以及将从信号处理器检测的极值产生时间点与对应于极值的参考时间点进行比较的控制器 产生时间点，并根据比较结果控制过程条件。
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公开(公告)号：US08841643B2
公开(公告)日：2014-09-23
申请号：US13241506
申请日：2011-09-23
Applicant: Gyu-Hwan Oh , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
Inventor： Gyu-Hwan Oh , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
CPC classification number: H01L45/06 , H01L27/224 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146
Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.
Abstract translation: 半导体器件包括设置在基板上的开关器件。 缓冲电极图案设置在开关装置上。 缓冲电极图案包括具有第一垂直厚度的第一区域和具有小于第一垂直厚度的第二垂直厚度的第二区域。 下部电极图案设置在缓冲电极图案的第一区域上。 修整绝缘图案设置在缓冲电极图案的第二区域上。 可变电阻图案设置在下电极图案上。
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6.发明申请SEMICONDUCTOR DEVICE INCLUDING BUFFER ELECTRODE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 有权包括缓冲电极的半导体器件，其制造方法以及包括其的存储器系统公开(公告)号：US20120119181A1
公开(公告)日：2012-05-17
申请号：US13241506
申请日：2011-09-23
Applicant: Gyu-Hwan OH , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
Inventor： Gyu-Hwan OH , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
IPC: H01L47/00
CPC classification number: H01L45/06 , H01L27/224 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146
Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.
Abstract translation: 半导体器件包括设置在基板上的开关器件。 缓冲电极图案设置在开关装置上。 缓冲电极图案包括具有第一垂直厚度的第一区域和具有小于第一垂直厚度的第二垂直厚度的第二区域。 下部电极图案设置在缓冲电极图案的第一区域上。 修整绝缘图案设置在缓冲电极图案的第二区域上。 可变电阻图案设置在下电极图案上。
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公开(公告)号：US08872059B2
公开(公告)日：2014-10-28
申请号：US13220084
申请日：2011-08-29
Applicant: Sang-Wuk Park , Geum-Jung Seong , Kye-Hyun Baek , Yong-Jin Kim , Chan-Mi Lee
Inventor： Sang-Wuk Park , Geum-Jung Seong , Kye-Hyun Baek , Yong-Jin Kim , Chan-Mi Lee
CPC classification number: B23K26/0661 , B23K26/032 , B23K26/361 , H01J37/32972 , H01L22/12 , H01L22/26
Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.
Abstract translation: 提供了蚀刻系统和控制蚀刻工艺条件的方法。 蚀刻系统包括将入射光照射到目标晶片中的光源，光强度测量单元，其根据由来自目标晶片的反射光之间的干涉产生的干涉光的波长来测量光强度;信号处理器，其检测 当干扰光的强度根据波长变化时产生强度极值的时间点，以及将从信号处理器检测的极值产生时间点与对应于极值的参考时间点进行比较的控制器 产生时间点，并根据比较结果控制过程条件。
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