公开(公告)号：US20220336233A1

公开(公告)日：2022-10-20

申请号：US17856039

申请日：2022-07-01

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu ,  Fei-Jain Wu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

公开(公告)号：US08796824B1

公开(公告)日：2014-08-05

申请号：US14014568

申请日：2013-08-30

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  Shyh-Jen Guo ,  You-Ming Hsu

IPC: H01L23/58 ,  H01L29/06 ,  H01L23/00 ,  H01L23/28 ,  H01L23/532

CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure having a first corner includes a carrier, a first protective layer, a second protective layer, and a third protective layer. The carrier comprises a carrier surface having a protection-layered disposing zone. The first protective layer comprises a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone, the second protective layer is disposed at the first disposing zone. The second protective layer comprises a second surface having a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner. An area of the first anti-stress zone is not smaller than that of the second anti-stress zone.

Abstract translation: 具有第一角的半导体结构包括载体，第一保护层，第二保护层和第三保护层。 载体包括具有保护层叠布置区的载体表面。 第一保护层包括具有第一布置区，第一抗应力区和第一曝光区的第一表面，第一抗应力区位于第一布置区的拐角处，第二保护层设置在 第一个处置区。 第二保护层包括具有第二设置区，第二抗应力区和第二曝光区的第二表面，第二抗应力区位于第二处置区的拐角处。 第一个抗应力区和第二个抗应力区位于第一个拐角处。 第一抗应力区域的面积不小于第二抗应力区域的面积。

公开(公告)号：US08963675B2

公开(公告)日：2015-02-24

申请号：US13644964

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00 ,  H01F27/28 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01F5/00 ,  H01F5/003 ,  H05K1/165 ,  H05K3/465 ,  H05K2201/097 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49155

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract translation: 一种制造具有三维电感器的载体的方法包括以下步骤：提供具有保护层的衬底; 在保护层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成第二开口和多个布置槽; 在第二开口中形成第一金属层并设置槽; 去除第一光致抗蚀剂层; 在所述保护层上形成第一介电层; 在所述第一介电层上形成第二光致抗蚀剂层; 图案化第二光致抗蚀剂层以形成多个槽; 在槽中形成第二金属层以形成多个感应部分; 去除所述第二光致抗蚀剂层; 在所述第一电介质层上形成第二电介质层; 在所述第二介电层上形成第三光致抗蚀剂层; 图案化第三光致抗蚀剂层以形成多个狭缝; 以及在槽中形成第三金属层。

公开(公告)号：US20130127578A1

公开(公告)日：2013-05-23

申请号：US13739210

申请日：2013-01-11

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00

CPC classification number: H01L23/48 ,  H01F5/00 ,  H01F5/003 ,  H01F17/0033 ,  H01F41/046 ,  H01L28/10

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

公开(公告)号：US20230170301A1

公开(公告)日：2023-06-01

申请号：US17972648

申请日：2022-10-25

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Chun-Ting Kuo ,  Lung-Hua Ho ,  Chih-Ming Kuo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/552

CPC classification number: H01L23/5286 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/552

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.

公开(公告)号：US20220037166A1

公开(公告)日：2022-02-03

申请号：US17161818

申请日：2021-01-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu ,  Fei-Jain Wu

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

公开(公告)号：US09000569B2

公开(公告)日：2015-04-07

申请号：US14042976

申请日：2013-10-01

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L21/4763 ,  H01L23/00 ,  H01L23/28 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。 第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上 投影线与第一底边相交形成第二交点。 通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。

公开(公告)号：US08981536B1

公开(公告)日：2015-03-17

申请号：US14048078

申请日：2013-10-08

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L29/06 ,  H01L23/58 ,  H01L23/495 ,  H01L23/00 ,  H01L29/02

CPC classification number: H01L23/562 ,  H01L23/31 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 第二保护层揭示第一抗应力区，并包括第二表面，第一横向侧，第二横向侧和第一连接侧。 第二表面包括第二抗应力区。 第一侧面的延伸线与第二侧面的延伸线相交形成第一交点。 通过连接第一交点和第一连接侧的两个点形成的区域是第一抗应力区域。 第三保护层显示第二抗应力区域，并且包括突出在第一表面上的第二连接侧，以形成平行于第一连接侧的突出线。

公开(公告)号：US20150069584A1

公开(公告)日：2015-03-12

申请号：US14042976

申请日：2013-10-01

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。 第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上 投影线与第一底边相交形成第二交点。 通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。

公开(公告)号：US20150091141A1

公开(公告)日：2015-04-02

申请号：US14048078

申请日：2013-10-08

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L23/00 ,  H01L29/02

CPC classification number: H01L23/562 ,  H01L23/31 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 第二保护层揭示第一抗应力区，并包括第二表面，第一横向侧，第二横向侧和第一连接侧。 第二表面包括第二抗应力区。 第一侧面的延伸线与第二侧面的延伸线相交形成第一交点。 通过连接第一交点和第一连接侧的两个点形成的区域是第一抗应力区域。 第三保护层显示第二抗应力区域，并且包括突出在第一表面上的第二连接侧，以形成平行于第一连接侧的突出线。