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    POWER MODE REGISTER REDUCTION AND POWER RAIL BRING UP ENHANCEMENT
    5.
    发明申请
    POWER MODE REGISTER REDUCTION AND POWER RAIL BRING UP ENHANCEMENT 有权
    电源模式注册减少和功率轨道增强

    公开(公告)号：US20140223153A1

    公开(公告)日：2014-08-07

    申请号：US13950738

    申请日：2013-07-25

    申请人： Broadcom Corporation

    发明人： Chih-Tsung Hsieh ,  Hao-zheng Lee ,  Walid Nabhane ,  Veronica Alarcon ,  Mark Norman Fullerton

    IPC分类号： G06F1/26

    CPC分类号： G06F11/1048 ,  G01R19/003 ,  G01R31/36 ,  G01R31/40 ,  G05F1/625 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/1016 ,  G06F11/3031 ,  G06F11/3058 ,  G06F11/3062 ,  G06F11/3093 ,  G06F13/126 ,  G11C7/106 ,  G11C7/1072 ,  H02J7/0029 ,  Y02D10/171

    摘要： Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner.

    摘要翻译： 描述了功率模式寄存器减少和电源轨的改进方案。 在一个实施例中，用于第一电力轨的操作参数由功率管理电路根据预定的编程设置来设置。 关于等待时间，电源轨已启用，并且处理器被释放以启动。 反过来，通过高速接口从处理器接收修改第一电力轨的操作参数的命令或用于设置第二电力轨的操作参数的命令中的至少一个。 通过访问一组电源轨的分组操作寄存器，处理器可以一次更新或修改整组电源轨的设置。 结合处理器，电源管理电路可以以灵活和有效的方式加电多个电源轨。

    CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPONSE CODES
    6.
    发明申请
    CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPONSE CODES 有权
    时钟交叉串行接口，直接锁定和响应代码

    公开(公告)号：US20140223031A1

    公开(公告)日：2014-08-07

    申请号：US13950713

    申请日：2013-07-25

    申请人： Broadcom Corporation

    发明人： Veronica Alarcon ,  Walid Nabhane ,  Mark Norman Fullerton ,  Love Kothari ,  Ronak Subhas Patel ,  Chih-Tsung Hsieh ,  Hao-zheng Lee

    IPC分类号： G06F13/12

    CPC分类号： G06F11/1048 ,  G01R19/003 ,  G01R31/36 ,  G01R31/40 ,  G05F1/625 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/1016 ,  G06F11/3031 ,  G06F11/3058 ,  G06F11/3062 ,  G06F11/3093 ,  G06F13/126 ,  G11C7/106 ,  G11C7/1072 ,  H02J7/0029 ,  Y02D10/171

    摘要： Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.

    摘要翻译： 描述串行接口的时钟域，串行接口上​​的直接锁存和响应代码的方面。 在各种实施例中，识别通过串行接口接收的数据通信命令，并且解析通过串行接口接收的地址以访问寄存器组。 在写操作中，根据地址是否落在寄存器组的直接锁存地址范围内，数据可以被直接锁存到寄存器组的直接锁存寄存器中或者先进先出寄存器。 对于读和写操作，可以参考串行接口的状态寄存器来识别或减轻错误状况，并且可以依赖等待时间来考虑时钟域穿越。 在每次读取和写入操作之后，可以传送包括状态指示器的响应代码。