公开(公告)号：US09026747B2

公开(公告)日：2015-05-05

申请号：US13718773

申请日：2012-12-18

Applicant: Broadcom Corporation

Inventor： Weihuang Wang ,  Chien-Hsien Wu ,  Mohammad Issa

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F12/02 ,  G06F12/06 ,  G11C8/00 ,  G11C7/10

CPC classification number: G06F12/0802 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/0853 ,  G06F2205/123 ,  G11C7/1075 ,  G11C8/00 ,  G11C2207/2245

Abstract: A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

Abstract translation: 本文描述了具有支持多个读取和写入访问的逻辑到物理（LTP）库映射缓存的存储器件。 存储器件允许在相同的时钟周期期间接收至少一个读取操作和一个写入操作。 在进入写入操作未被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在对应于与输入写入操作相关联的逻辑存储器组的物理存储体中。 在进入写入操作被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在未与任何逻辑存储体相关联的未映射的物理存储体中。

公开(公告)号：US09003121B2

公开(公告)日：2015-04-07

申请号：US13655723

申请日：2012-10-19

Applicant: Broadcom Corporation

Inventor： Weihuang Wang ,  Chien-Hsien Wu

IPC: G06F12/00 ,  G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0853 ,  G11C7/1075 ,  G11C2207/2245 ,  Y02D10/13

Abstract: A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

Abstract translation: 本文描述了支持多个读取和写入访问的多端口存储器。 多端口存储器可以包括大于多端口存储器的每个存储器组的读/写端口的数量的读/写端口。 多端口存储器允许在相同时钟周期期间接收至少一个读取操作和至少一个写入操作。 在进入写入操作被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在多端口存储器中包括的高速缓存中。 该缓存对于写操作和读操作均可访问。 在进入写入操作不被至少一个读取操作阻止的情况下，用于该输入写入操作的数据被存储在由该输入写入操作所针对的存储体中。

公开(公告)号：US20140052912A1

公开(公告)日：2014-02-20

申请号：US13718773

申请日：2012-12-18

Applicant: BROADCOM CORPORATION

Inventor： Weihuang Wang ,  Chien-Hsien Wu ,  Mohammad Issa

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/0853 ,  G06F2205/123 ,  G11C7/1075 ,  G11C8/00 ,  G11C2207/2245

Abstract: A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

Abstract translation: 本文描述了具有支持多个读取和写入访问的逻辑到物理（LTP）库映射缓存的存储器件。 存储器件允许在相同的时钟周期期间接收至少一个读取操作和一个写入操作。 在进入写入操作未被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在对应于与输入写入操作相关联的逻辑存储器组的物理存储体中。 在进入写入操作被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在未与任何逻辑存储体相关联的未映射的物理存储体中。

公开(公告)号：US09128850B2

公开(公告)日：2015-09-08

申请号：US13716605

申请日：2012-12-17

Applicant: Broadcom Corporation

Inventor： Weihuang Wang ,  Chien-Hsien Wu

IPC: G06F12/08

CPC classification number: G06F12/0846 ,  G06F12/0853 ,  Y02D10/13

Abstract: A multi-ported memory that supports multiple read and write accesses is described. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for read operation(s) and write operation(s) to be received during the same clock cycle. In the event that an incoming write operation is blocked by read operation(s), data for that write operation may be stored in one of a plurality of cache banks included in the multi-port memory. The cache banks are accessible to both write and read operations. In the event than the write operation is not blocked by read operation(s), a determination is made as to whether data for that incoming write operation is stored in the memory bank targeted by that incoming write operation or in one of the cache banks.

Abstract translation: 描述了支持多个读写访问的多端口存储器。 多端口存储器可以包括大于多端口存储器的每个存储器组的读/写端口的数量的读/写端口。 多端口存储器允许在同一时钟周期期间接收读操作和写操作。 在传入写入操作被读取操作阻止的情况下，用于该写入操作的数据可以存储在多端口存储器中包括的多个高速缓冲存储器之一中。 高速缓冲存储区可以在写操作和读操作两者中访问。 在写入操作不被读取操作阻止的情况下，确定用于该输入写入操作的数据是否存储在由该输入写入操作所针对的存储体中或者在一个缓存存储体中。

公开(公告)号：US20140052914A1

公开(公告)日：2014-02-20

申请号：US13716605

申请日：2012-12-17

Applicant: BROADCOM CORPORATION

Inventor： Weihuang Wang ,  Chien-Hsien Wu

IPC: G06F12/08

CPC classification number: G06F12/0846 ,  G06F12/0853 ,  Y02D10/13

Abstract: A multi-ported memory that supports multiple read and write accesses is described. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for read operation(s) and write operation(s) to be received during the same clock cycle. In the event that an incoming write operation is blocked by read operation(s), data for that write operation may be stored in one of a plurality of cache banks included in the multi-port memory. The cache banks are accessible to both write and read operations. In the event than the write operation is not blocked by read operation(s), a determination is made as to whether data for that incoming write operation is stored in the memory bank targeted by that incoming write operation or in one of the cache banks.

Abstract translation: 描述了支持多个读写访问的多端口存储器。 多端口存储器可以包括大于多端口存储器的每个存储器组的读/写端口的数量的读/写端口。 多端口存储器允许在同一时钟周期期间接收读操作和写操作。 在传入写入操作被读取操作阻止的情况下，用于该写入操作的数据可以存储在多端口存储器中包括的多个高速缓冲存储器之一中。 高速缓冲存储区可以在写操作和读操作两者中访问。 在写入操作不被读取操作阻止的情况下，确定用于该输入写入操作的数据是否存储在由该输入写入操作所针对的存储体中或者在一个缓存存储体中。

公开(公告)号：US20140052913A1

公开(公告)日：2014-02-20

申请号：US13655723

申请日：2012-10-19

Applicant: BROADCOM CORPORATION

Inventor： Weihuang Wang ,  Chien-Hsien Wu

IPC: G06F12/08

CPC classification number: G06F12/0853 ,  G11C7/1075 ,  G11C2207/2245 ,  Y02D10/13

Abstract: A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

Abstract translation: 本文描述了支持多个读取和写入访问的多端口存储器。 多端口存储器可以包括大于多端口存储器的每个存储器组的读/写端口的数量的读/写端口。 多端口存储器允许在相同时钟周期期间接收至少一个读取操作和至少一个写入操作。 在进入写入操作被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在多端口存储器中包括的高速缓存中。 该缓存对于写操作和读操作均可访问。 在进入写入操作不被至少一个读取操作阻止的情况下，用于该输入写入操作的数据被存储在由该输入写入操作所针对的存储体中。