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公开(公告)号：US20250124841A1
公开(公告)日：2025-04-17
申请号：US18291452
申请日：2023-03-31
Inventor： Can YUAN , Yongqian LI , Miao LIU , Dandan ZHOU , Cheng XU
IPC: G09G3/20
Abstract: A driving circuit includes a pull-up node control circuit, a pull-down node control circuit and an output circuit; the pull-up node control circuit controls a potential of the pull-up node under the control of an input signal and a reset signal; the output circuit controls the output terminal to output a signal under the control of the potential of the pull-up node and the potential of the pull-down node; a channel length of at least one transistor among at least some transistors included in the output circuit, at least some transistors whose gate electrodes are electrically connected to the input terminal included in the pull-up node control circuit, and at least some transistors whose gate electrodes are electrically connected to the reset terminal included in the pull-up node control circuit is greater than a channel length of another transistor included in the driving circuit.
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公开(公告)号：US20250006121A1
公开(公告)日：2025-01-02
申请号：US18275228
申请日：2022-07-28
IPC: G09G3/3225 , G09G3/32
Abstract: Provided is a compensation method for a display device. The method includes: acquiring first detection voltages of the plurality of subpixels during a first shutdown compensation process; acquiring first position indication information based on the first detection voltages of the plurality of subpixels; and determining first compensation data based on the first position indication information. The first position indication information indicates column positions of pixels to which a plurality of first subpixels of the plurality of subpixels belong. The first compensation data includes first threshold compensation voltages of the plurality of subpixels, and an absolute value of a difference between the first threshold compensation voltage of the first subpixel and a first reference value is less than an absolute value of a difference between a second threshold compensation voltage of the first subpixel in the first compensation data and the first reference value.
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公开(公告)号：US20240402966A1
公开(公告)日：2024-12-05
申请号：US18261152
申请日：2022-06-29
Inventor： Xiaolong WEI , Wenchao BAO , Song MENG , Yao ZHANG , Miao LIU , Cheng XU , Jingbo XU
IPC: G06F3/14
Abstract: A display device includes: a display screen, a drive circuit, a first controller and a second controller. The display screen includes a first display region and a second display region. The drive circuit is configured to transmit a control signal to at least one of the first controller or the second controller. The first controller is configured to, responding to the control signal, perform a display control on the first display region. The second controller is configured to, responding to the control signal, perform a display control on the second display region. A display time difference between the first display region and the second display region is less than a threshold time period.
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公开(公告)号：US20220291537A1
公开(公告)日：2022-09-15
申请号：US17512634
申请日：2021-10-27
Inventor： Zhuolong LI , Yu ZHANG , Guangyun TONG , Liang BO , Miao LIU , Xuefei QIN
IPC: G02F1/133 , G02F1/1333 , G02F1/1347
Abstract: A display device is disclosed, which includes a display screen and a dimming screen which are arranged in a stacked manner, a backlight module on a side of the dimming screen away from the display screen, and a circuit board module on a side of the backlight module away from the dimming screen. The circuit board module includes a first control circuit board on the side of the backlight module away from the dimming screen and a second control circuit board on a side of the first control circuit board away from the backlight module, the first control circuit board is electrically connected with the dimming screen through a first Chip On Film and the second control circuit board is electrically connected with the display screen through a second Chip On Film. The circuit board module further includes a first support frame and a second support frame.
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公开(公告)号：US20250166573A1
公开(公告)日：2025-05-22
申请号：US18290493
申请日：2023-02-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chengyuan LUO , Pan XU , Ying HAN , Donghui ZHAO , Xing ZHANG , Guangshuang LV , Cheng XU , Xing YAO , Dandan ZHOU , Miao LIU
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: A shift register is provided to include: a voltage regulating circuit to adjust voltages at first and second nodes; a light-emitting cascade output circuit to write a second operating voltage from a second power terminal to a light-emitting cascade signal output terminal in response to control of the voltage at the first node, and write a first operating voltage from a first power terminal to the light-emitting cascade signal output terminal in response to control of the voltage at the second node; a light-emitting driving output circuit to write a third operating voltage from a third power terminal to a light-emitting control driving signal output terminal in response to control of the voltage at the first node, and write a fifth operating voltage from a fifth power terminal to the light-emitting control driving signal output terminal in response to control of the voltage at the second node; and a first anti-leakage circuit to write a fourth operating voltage from a fourth power terminal to a first anti-leakage node in response to control of the voltage at the second node.
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Patent Agency Ranking
公开(公告)号：US20250095536A1
公开(公告)日：2025-03-20
申请号：US18290015
申请日：2022-11-23
Applicant: BOE Technology Group Co., Ltd.
Inventor： Donghui ZHAO , Pan XU , Ying HAN , Xing ZHANG , Chengyuan LUO , Guangshuang LV , Xing YAO , Dandan ZHOU , Miao LIU
IPC: G09G3/20
Abstract: Provided is a pixel drive circuit. The pixel drive circuit includes a plurality of scan drive circuits transmitting gate drive signals to pixels, a plurality of emission drive circuits transmitting emission control signals to the pixels, a plurality of compensation drive circuits transmitting compensation signals to the pixels, and a plurality of reset drive circuits transmitting reset signals to the pixels, which are all cascaded in a pixel column direction. In addition, the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit corresponding to the same row of pixels are arranged sequentially along a pixel row direction, the scan drive circuit being disposed farthest away from the pixels. Moreover, among signal lines coupled to the pixel drive circuit, a plurality of signal lines is overlapped with each other, and cutouts are provided at the overlapping portions of the plurality of signal lines.
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公开(公告)号：US20250095524A1
公开(公告)日：2025-03-20
申请号：US18557312
申请日：2022-10-27
IPC: G09G3/00 , G09G3/32 , G09G3/3266 , G09G3/3275
Abstract: A display module includes sub-pixels, data lines, a source driving circuit and a processor. Each sub-pixel includes light-emitting sub-units each including a pixel circuit and at least one light-emitting device. A data line is electrically connected to a sub-pixel. The source driving circuit is electrically connected to the data line. The source driving circuit is configured to output a first or second data signal to the sub-pixel through the data line. The processor is configured to: determine location information of a target sub-pixel; and control, according to the location information, the source driving circuit to output the second data signal to the target sub-pixel, so that a brightness of the target sub-pixel is substantially the same as that of a non-target sub-pixel.
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公开(公告)号：US20250029558A1
公开(公告)日：2025-01-23
申请号：US18281110
申请日：2022-11-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xing ZHANG , Pan XU , Donghui ZHAO , Ying HAN , Chengyuan LUO , Guangshuang LV , Cheng XU , Miao LIU , Dandan ZHOU
IPC: G09G3/3233
Abstract: A driving circuit, a driving method and a display device are provided. The driving circuit includes a first control node control circuit, a second control node control circuit, a first node control circuit and a second node control circuit, wherein, the first control node control circuit is configured to control a potential of the first control node; the second control node control circuit is configured to control a potential of the second control node; the first node control circuit is configured to control a potential of the first node; the second node control circuit is electrically connected to the second control node, a first clock signal terminal and a second node respectively, and is configured to control to connect the first clock signal terminal and the second node under the control of the potential of the second control node.
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公开(公告)号：US20250014520A1
公开(公告)日：2025-01-09
申请号：US18272595
申请日：2022-07-28
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Liu WU , Luke DING , Cheng XU , Miao LIU , Xing YAO
IPC: G09G3/3266 , G11C19/28
Abstract: Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.
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公开(公告)号：US20250006134A1
公开(公告)日：2025-01-02
申请号：US18277375
申请日：2022-07-25
Inventor： Xuehuan FENG , Jingbo XU , Xing YAO , Miao LIU
IPC: G09G3/3266 , G11C19/28
Abstract: There is provided a shift register unit, including: a sensing control circuit configured to write an active level signal provided by a sensing active level supply terminal to a first sensing control node in response to an active level signal provided by the random signal input terminal and an active level signal provided by a sensing signal input terminal; a first sensing input circuit configured to write an active level signal to a first pull-up node in response to an active level signal at the first sensing control node and an active level signal provided by a clock control signal input terminal; and a first driving output circuit configured to write a signal provided by a first driving clock signal input terminal to a first driving signal output terminal in response to an active level signal at the first pull-up node. Gate driving circuit and method are further disclosed.
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