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公开(公告)号：US20210358381A1
公开(公告)日：2021-11-18
申请号：US16336546
申请日：2018-08-14
发明人： Zhichong WANG , Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Lijun YUAN , Xing YAO , Mingfu HAN
IPC分类号： G09G3/20
摘要： Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal.
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公开(公告)号：US20210225312A1
公开(公告)日：2021-07-22
申请号：US16307060
申请日：2018-06-07
发明人： Mingfu HAN , Guangliang SHANG , Seung Woo HAN , Xing YAO , Haoliang ZHENG , Lijun YUAN , Zhichong WANG
摘要： A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a pull-up node reset circuit, an output circuit and a coupling circuit. The input circuit is configured to charge a pull-up node in response to an input signal; the pull-up node reset circuit is configured to reset the pull-up node in response to a reset signal; the output circuit is configured to output a first clock signal to a first output terminal under control of a level of the pull-up node; and the coupling circuit is configured to control, by coupling, a potential of the pull-up node in response to a second clock signal.
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公开(公告)号：US20180350315A1
公开(公告)日：2018-12-06
申请号：US15513952
申请日：2016-02-29
发明人： Yuanbo ZHANG , Seungwoo HAN , Xing YAO
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/36 , G09G2310/06 , G09G2330/021
摘要： The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.
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公开(公告)号：US20160274432A1
公开(公告)日：2016-09-22
申请号：US14409217
申请日：2014-06-30
发明人： Xing YAO
IPC分类号： G02F1/1362 , G02F1/1339 , H01L27/12 , G02F1/1368
CPC分类号： G02F1/136286 , G02F1/13394 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L27/124 , H01L27/1248
摘要： An array substrate and a display device having the array substrate are provided. The array substrate comprises a display region and a non-display region disposed at the periphery of the display region. The non-display region comprises a gate driver region (GOA region), which comprises a first patterned metal layer formed on a base substrate, a first insulating layer formed on the first patterned metal layer, a second patterned metal layer formed on the first insulating layer, a second insulating layer covering the second patterned metal layer, and a third patterned metal layer formed at a side of the second insulating layer away from the base substrate. The third patterned metal layer comprises a plurality of metal wires insulated from each other and connected to the first patterned metal layer and the second patterned metal layer respectively by through holes and used as connecting lines between elements of the gate driver.
摘要翻译： 提供阵列基板和具有阵列基板的显示装置。 阵列基板包括设置在显示区域周边的显示区域和非显示区域。 非显示区域包括栅极驱动器区域（GOA区域），其包括形成在基底衬底上的第一图案化金属层，形成在第一图案化金属层上的第一绝缘层，形成在第一绝缘层上的第二图案化金属层 层，覆盖第二图案化金属层的第二绝缘层和形成在第二绝缘层的远离基底的一侧的第三图案化金属层。 第三图案化金属层包括彼此绝缘并且分别通过通孔连接到第一图案化金属层和第二图案化金属层的多个金属线，并且用作栅极驱动器的元件之间的连接线。
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公开(公告)号：US20240312419A1
公开(公告)日：2024-09-19
申请号：US18620521
申请日：2024-03-28
发明人： Xing YAO , Chen XU , Jingquan WANG , Xinyin WU
IPC分类号： G09G3/3266 , H10K59/126 , H10K59/131
CPC分类号： G09G3/3266 , H10K59/126 , H10K59/131 , G09G2300/0426 , G09G2310/0286
摘要： A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, a gate scan driving circuit, a light-emitting control scan driving circuit, a first power line, a first planarization layer, a second planarization layer and a first shielding layer and a second shielding layer. The first planarization layer and the second planarization layer further include an open slot. The second shielding layer extends from a region corresponding to the light-emitting control scan driving circuit to a region corresponding to the gate scan driving circuit and covers the open slot. In an area where the second shielding layer is close to the open slot, an orthographic projection of the second shielding layer covering the open slot on the base substrate at least overlaps with an orthographic projection of the first shielding layer on the base substrate.
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公开(公告)号：US20190356523A1
公开(公告)日：2019-11-21
申请号：US16414478
申请日：2019-05-16
发明人： Lijun YUAN , Haoliang ZHENG , Guangliang SHANG , Xing YAO , Mingfu HAN
摘要： A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.
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公开(公告)号：US20190279588A1
公开(公告)日：2019-09-12
申请号：US16066827
申请日：2017-12-14
发明人： Jiha KIM , Lijun YUAN , Zhichong WANG , Mingfu HAN , Xing YAO , Guangliang SHANG , Seung Woo HAN , Yun Sik IM , Jing LV , Yinglong HUANG , Jung Mok JUN , Haoliang ZHENG
摘要： There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.
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8.发明申请公开(公告)号：US20190027079A1
公开(公告)日：2019-01-24
申请号：US15577402
申请日：2017-05-03
发明人： Guangliang SHANG , Xing YAO , Mingfu HAN , Seung-Woo HAN , Yun-Sik IM , Jing LV , Yinglong HUANG , Jung-Mok JUN , Xue DONG , Haoliang ZHENG , Lijun YUAN , Zhichong WANG , Ji Ha KIM
摘要： A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.
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9.发明申请公开(公告)号：US20180108289A1
公开(公告)日：2018-04-19
申请号：US15502983
申请日：2016-05-19
发明人： Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Hyunsic CHOI , Mingfu HAN , Xing YAO , Zhichong WANG , Lijun YUAN
CPC分类号： G09G3/2092 , G09G3/20 , G09G2300/0408 , G09G2300/0871 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/02 , G11C19/28
摘要： The present disclosure relates to a shift register unit and driving method thereof, a gate driving circuit and a display device. The shift register unit comprises: an input module for controlling a level of a first node based on a scan pulse, an output module for controlling a scan pulse output based on the level of the first node, a reset module for resetting the first node and the scan pulse output, and a control module for generating a reset trigger signal, wherein the reset module further resets the first node based on the reset trigger signal. The shift register units can be cascaded to form a gate driving circuit to realize output of multiple scan pulses. By integrating such a gate driving circuit on the array substrate, area of the bezel region of the array substrate can be reduced, thereby facilitating bezel narrowing of a display device. At the same time, due to presence of the control module, the reset module is enabled to reset the first node more stably while normal output of the scan pulse is maintained.
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公开(公告)号：US20240304266A1
公开(公告)日：2024-09-12
申请号：US18245030
申请日：2022-05-26
发明人： Jiangnan LU , Guangliang SHANG , Jianchao ZHU , Zhenzhen SHAN , Xing YAO
IPC分类号： G11C19/28 , G09G3/3225
CPC分类号： G11C19/287 , G09G3/3225 , G09G2300/0426 , G09G2310/0286
摘要： A shift register unit includes: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a drive output terminal in response to a signal of the first node, and provide a second reference signal to the drive output terminal in response to a signal of the second node; where a duration of an active level of the first control signal is longer than a duration of an active level of a signal of the drive output terminal.
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