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公开(公告)号：US20210358381A1
公开(公告)日：2021-11-18
申请号：US16336546
申请日：2018-08-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhichong WANG , Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Lijun YUAN , Xing YAO , Mingfu HAN
IPC: G09G3/20
Abstract: Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal.
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公开(公告)号：US20210225312A1
公开(公告)日：2021-07-22
申请号：US16307060
申请日：2018-06-07
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Mingfu HAN , Guangliang SHANG , Seung Woo HAN , Xing YAO , Haoliang ZHENG , Lijun YUAN , Zhichong WANG
Abstract: A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a pull-up node reset circuit, an output circuit and a coupling circuit. The input circuit is configured to charge a pull-up node in response to an input signal; the pull-up node reset circuit is configured to reset the pull-up node in response to a reset signal; the output circuit is configured to output a first clock signal to a first output terminal under control of a level of the pull-up node; and the coupling circuit is configured to control, by coupling, a potential of the pull-up node in response to a second clock signal.
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公开(公告)号：US20180350315A1
公开(公告)日：2018-12-06
申请号：US15513952
申请日：2016-02-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yuanbo ZHANG , Seungwoo HAN , Xing YAO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G2310/06 , G09G2330/021
Abstract: The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.
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公开(公告)号：US20160274432A1
公开(公告)日：2016-09-22
申请号：US14409217
申请日：2014-06-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xing YAO
IPC: G02F1/1362 , G02F1/1339 , H01L27/12 , G02F1/1368
CPC classification number: G02F1/136286 , G02F1/13394 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L27/124 , H01L27/1248
Abstract: An array substrate and a display device having the array substrate are provided. The array substrate comprises a display region and a non-display region disposed at the periphery of the display region. The non-display region comprises a gate driver region (GOA region), which comprises a first patterned metal layer formed on a base substrate, a first insulating layer formed on the first patterned metal layer, a second patterned metal layer formed on the first insulating layer, a second insulating layer covering the second patterned metal layer, and a third patterned metal layer formed at a side of the second insulating layer away from the base substrate. The third patterned metal layer comprises a plurality of metal wires insulated from each other and connected to the first patterned metal layer and the second patterned metal layer respectively by through holes and used as connecting lines between elements of the gate driver.
Abstract translation: 提供阵列基板和具有阵列基板的显示装置。 阵列基板包括设置在显示区域周边的显示区域和非显示区域。 非显示区域包括栅极驱动器区域（GOA区域），其包括形成在基底衬底上的第一图案化金属层，形成在第一图案化金属层上的第一绝缘层，形成在第一绝缘层上的第二图案化金属层 层，覆盖第二图案化金属层的第二绝缘层和形成在第二绝缘层的远离基底的一侧的第三图案化金属层。 第三图案化金属层包括彼此绝缘并且分别通过通孔连接到第一图案化金属层和第二图案化金属层的多个金属线，并且用作栅极驱动器的元件之间的连接线。
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公开(公告)号：US20250104646A1
公开(公告)日：2025-03-27
申请号：US18558905
申请日：2023-01-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chengyuan LUO , Pan XU , Ying HAN , Xing ZHANG , Donghui ZHAO , Guangshuang LV , Cheng XU , Xing YAO , Dandan ZHOU , Miao LIU
IPC: G09G3/3266
Abstract: A driving circuit, a driving module, a driving method, a display substrate and a display device are provided. The driving circuit includes a first leakage prevention circuit, an output circuit and a first control node control circuit; the first leakage prevention circuit is configured to control to connect or disconnect the first control node, the first node and the first intermediate node under the control of a first voltage signal provided by the first voltage line according to a potential of the first intermediate node, control to connect or disconnect the first intermediate node and the second voltage line under the control of the potential of the first node, and control to disconnect the first control node and the first node when the first intermediate node and the second voltage line is connected.
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Patent Agency Ranking
公开(公告)号：US20250087149A1
公开(公告)日：2025-03-13
申请号：US18288454
申请日：2022-12-15
Inventor： Kening ZHENG , Xueguang HAO , Xing YAO
IPC: G09G3/3233
Abstract: The present disclosure provides a display panel and a display apparatus, and belongs to the field of display technology, and can solve the problem of the color shift easily occurring in the high-temperature reliability test in the related display panel. The display panel of the present disclosure includes: a plurality of sub-pixel units and a voltage control module; each sub-pixel unit includes: a light emitting device; and the voltage control module is connected to an anode of the corresponding light emitting device, and is configured to control an anode voltage of the corresponding light emitting device, so that a ratio of the number of electrons to the number of holes of the light emitting device is unchanged at different gray scales.
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公开(公告)号：US20250078757A1
公开(公告)日：2025-03-06
申请号：US18951223
申请日：2024-11-18
Inventor： Gansong YANG , Yunpeng ZHANG , Ming YANG , Yanhong DING , Ke LIU , Miao LIU , Xing YAO
IPC: G09G3/3233 , G09G3/3266
Abstract: A display substrate is provided to include: a base substrate including a display area and a peripheral area surrounding the display area; pixel units in array are in the display area; a driving module is in the peripheral area and is configured to provide electrical signals for the pixel units, to control the pixel units to operate; the driving module includes driving circuits each provided with a corresponding operating signal line group in the peripheral area; the signal line group includes at least two operating signal lines connected to the corresponding driving circuit, to provide electrical signals thereto; the at least two operating signal lines include first and second clock signal lines; the first clock signal lines for at least two driving circuits are a same first clock signal line; and/or the second clock signal lines for the at least two driving circuits are a same second clock signal line.
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公开(公告)号：US20240395201A1
公开(公告)日：2024-11-28
申请号：US18272811
申请日：2022-07-29
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Liu WU , Xiuting LIU , Luke DING , Cheng XU , Miao LIU , Xing YAO
IPC: G09G3/3233 , G11C19/28 , H10K59/131
Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.
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公开(公告)号：US20240312419A1
公开(公告)日：2024-09-19
申请号：US18620521
申请日：2024-03-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xing YAO , Chen XU , Jingquan WANG , Xinyin WU
IPC: G09G3/3266 , H10K59/126 , H10K59/131
CPC classification number: G09G3/3266 , H10K59/126 , H10K59/131 , G09G2300/0426 , G09G2310/0286
Abstract: A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, a gate scan driving circuit, a light-emitting control scan driving circuit, a first power line, a first planarization layer, a second planarization layer and a first shielding layer and a second shielding layer. The first planarization layer and the second planarization layer further include an open slot. The second shielding layer extends from a region corresponding to the light-emitting control scan driving circuit to a region corresponding to the gate scan driving circuit and covers the open slot. In an area where the second shielding layer is close to the open slot, an orthographic projection of the second shielding layer covering the open slot on the base substrate at least overlaps with an orthographic projection of the first shielding layer on the base substrate.
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公开(公告)号：US20190356523A1
公开(公告)日：2019-11-21
申请号：US16414478
申请日：2019-05-16
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Lijun YUAN , Haoliang ZHENG , Guangliang SHANG , Xing YAO , Mingfu HAN
Abstract: A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.
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