公开(公告)号：US20160260788A1

公开(公告)日：2016-09-08

申请号：US14435895

申请日：2014-08-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jingfei Fang ,  Chunsheng Jiang ,  Yanzhao Li

IPC: H01L27/32 ,  H01L51/56

CPC classification number: H01L27/3248 ,  H01L27/1288 ,  H01L27/322 ,  H01L27/3258 ,  H01L51/5206 ,  H01L51/56 ,  H01L2227/323

Abstract: The present invention discloses a WOLED back panel and a method of manufacturing the same. The method comprises: forming a pattern of a color filter layer on a substrate; exposing the pattern of the color filter layer by halftone exposure so as to form a groove structure in the pattern of the color filter layer; forming a pattern of a resin material layer on a surface of the substrate formed with the groove structure, and heavily doping a partial region of the resin material layer so as to form a heavily doped part having a conductivity; the heavily doped partial region of the resin material layer corresponding to a pixel electrode region, a via region, and a connection region between the pixel electrode region and the via region; and forming an organic light-emitting layer and a cathode in order on a surface of the substrate after heavily doping the partial region of the resin material layer. The production cost is reduced in the present invention by forming a groove structure in the color filter layer instead of manufacturing a conventional pixel defining layer.

Abstract translation: 本发明公开了一种WOLED背面板及其制造方法。 该方法包括：在衬底上形成滤色器层的图案; 通过半色调曝光曝光滤色器层的图案，以便在滤色器层的图案中形成凹槽结构; 在形成有槽结构的基板的表面上形成树脂材料层的图案，并且重掺杂树脂材料层的部分区域，以形成具有导电性的重掺杂部分; 对应于像素电极区域，通孔区域和像素电极区域和通孔区域之间的连接区域的树脂材料层的重掺杂部分区域; 以及在重掺杂树脂材料层的部分区域之后，在衬底的表面上依次形成有机发光层和阴极。 通过在滤色器层中形成凹槽结构而不是制造常规的像素限定层，在本发明中降低了生产成本。

公开(公告)号：US09397223B2

公开(公告)日：2016-07-19

申请号：US14347124

申请日：2013-12-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunsheng Jiang ,  Jingfei Fang

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/66969

Abstract: Embodiments of the invention provide a thin film transistor, a method of manufacturing the same, an array substrate comprising the thin film transistor and a display device. The method of manufacturing the thin film transistor comprises steps of forming a gate electrode (220), a gate insulating layer (230), an oxide active layer (240), a source electrode (260) and a drain electrode (270) on a substrate (210). After forming the oxide active layer (240), the method further comprises a step of forming an etch barrier layer (250) of a metal oxide on the oxide active layer (240).

Abstract translation: 本发明的实施例提供一种薄膜晶体管，其制造方法，包括薄膜晶体管的阵列基板和显示装置。 制造薄膜晶体管的方法包括以下步骤：在栅极电极（220），栅极绝缘层（230），氧化物活性层（240），源极（260）和漏极（270）上形成 衬底（210）。 在形成氧化物活性层（240）之后，该方法还包括在氧化物活性层（240）上形成金属氧化物的蚀刻阻挡层（250）的步骤。

公开(公告)号：US09691836B2

公开(公告)日：2017-06-27

申请号：US14769456

申请日：2014-12-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunsheng Jiang ,  Jingfei Fang ,  Baojiang Zhang

IPC: H01L29/08 ,  H01L27/32 ,  H01L51/56 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L27/3274 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/4908 ,  H01L29/7869 ,  H01L51/56

Abstract: A pixel unit is used in an array substrate of a display device. In one embodiment, it comprises a gate line, a source-drain line and a thin-film transistor; and the gate line is in an overlapped structure comprising a first MoW layer, a Cu layer and a second MoW layer overlapped successively; and a gate of the thin-film transistor is formed of the first MoW layer. In another embodiment, the source-drain line is in a same overlapped structure; and a source and a drain of the thin-film transistor are formed of the first MoW layer. The first embodiment is achieved by means of a halftone process while the second embodiment is achieved by means of a lift off process. Diffusion of Cu in the gate layer or in the source-drain layer towards the oxide active layer is prevented. Also disclosed is a method for manufacturing the abovementioned pixel unit, an array substrate comprising the abovementioned pixel unit, a display device comprising the abovementioned pixel unit, and a method for manufacturing abovementioned array substrate and display device.

公开(公告)号：US20150171219A1

公开(公告)日：2015-06-18

申请号：US14347124

申请日：2013-12-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunsheng Jiang ,  Jingfei Fang

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/66969

Abstract: Embodiments of the invention provide a thin film transistor, a method of manufacturing the same, an array substrate comprising the thin film transistor and a display device. The method of manufacturing the thin film transistor comprises steps of forming a gate electrode (220), a gate insulating layer (230), an oxide active layer (240), a source electrode (260) and a drain electrode (270) on a substrate (210). After forming the oxide active layer (240), the method further comprises a step of forming an etch barrier layer (250) of a metal oxide on the oxide active layer (240).

Abstract translation: 本发明的实施例提供一种薄膜晶体管，其制造方法，包括薄膜晶体管的阵列基板和显示装置。 制造薄膜晶体管的方法包括以下步骤：在栅极电极（220），栅极绝缘层（230），氧化物活性层（240），源极（260）和漏极（270）上形成 衬底（210）。 在形成氧化物活性层（240）之后，该方法还包括在氧化物活性层（240）上形成金属氧化物的蚀刻阻挡层（250）的步骤。

公开(公告)号：US09882172B2

公开(公告)日：2018-01-30

申请号：US14429047

申请日：2014-07-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunsheng Jiang ,  Jingfei Fang ,  Wei Liu

IPC: H01L51/56 ,  H01L51/52 ,  H01L27/32

CPC classification number: H01L51/56 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3258 ,  H01L51/5206 ,  H01L51/5237

Abstract: Disclosed are an OLED backplane and fabrication method. The fabrication method comprises: forming a pattern including a TFT on a substrate; forming a passivation layer on the substrate including the TFT pattern; forming a color filter on the substrate including the passivation layer; forming a resin layer on the substrate including the color filter; heavily doping the resin layer of a first region in each sub-pixel on the substrate including the resin layer, the resin layer in the first region being conductive, the first region including a passivation layer via-hole region, a pixel electrode region and a connecting region between the passivation layer via-hole region and the pixel electrode region, the passivation-layer via-hole region being a position where a drain electrode of the TFT is located; and forming an organic light-emitting layer and a cathode sequentially on the substrate after the resin layer of the first region is heavily doped.

公开(公告)号：US09704998B2

公开(公告)日：2017-07-11

申请号：US14653134

申请日：2014-08-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jingfei Fang ,  Chunsheng Jiang

IPC: H01L29/786 ,  H01L21/477 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention discloses a thin film transistor, a method of manufacturing the thin film transistor, a display substrate and a display apparatus. The method comprising steps of: forming an active material layer on a substrate; forming an etch barrier material layer on the active material layer, wherein the etch barrier material layer being made of a conductive material capable of blocking a source and drain etching liquid; forming an active layer pattern and an initial etch barrier layer pattern by performing a single patterning process on the active material layer and the etch barrier material layer, wherein the initial etch barrier layer pattern comprising a first region, a second region and a third region, the first region and the third region being regions for forming a source and a drain, respectively, the second region being a region of the initial etch barrier layer pattern except the first and third regions; forming the source and the drain in the first region and the third region, respectively, by a patterning process; converting the conductive material in the second region of the initial etch barrier layer pattern into an insulation material by an annealing process, so as to form an etch barrier layer.

公开(公告)号：US09679953B2

公开(公告)日：2017-06-13

申请号：US14435895

申请日：2014-08-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jingfei Fang ,  Chunsheng Jiang ,  Yanzhao Li

IPC: H01L27/32 ,  H01L27/12 ,  H01L51/52 ,  H01L51/56

CPC classification number: H01L27/3248 ,  H01L27/1288 ,  H01L27/322 ,  H01L27/3258 ,  H01L51/5206 ,  H01L51/56 ,  H01L2227/323

Abstract: The present invention discloses a WOLED back panel and a method of manufacturing the same. The method comprises: forming a pattern of a color filter layer on a substrate; exposing the pattern of the color filter layer by halftone exposure so as to form a groove structure in the pattern of the color filter layer; forming a pattern of a resin material layer on a surface of the substrate formed with the groove structure, and heavily doping a partial region of the resin material layer so as to form a heavily doped part having a conductivity; the heavily doped partial region of the resin material layer corresponding to a pixel electrode region, a via region, and a connection region between the pixel electrode region and the via region; and forming an organic light-emitting layer and a cathode in order on a surface of the substrate after heavily doping the partial region of the resin material layer. The production cost is reduced in the present invention by forming a groove structure in the color filter layer instead of manufacturing a conventional pixel defining layer.