公开(公告)号：US09847357B2

公开(公告)日：2017-12-19

申请号：US15085134

申请日：2016-03-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yucheng Chan ,  Chienhung Liu

IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1248 ,  H01L21/02183 ,  H01L21/02244 ,  H01L27/1259 ,  H01L29/08 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78606

Abstract: The present invention belongs to the field of display technology and provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a gate, a source, a drain and a plurality of insulating layers, wherein at least one insulating layer comprises a Group VB metal oxide. Since the insulting layer is formed by using the Group VB metal oxide which has high dielectric constant, the thickness of the insulating layer can be reduced and the thin film transistor can be miniaturized.

公开(公告)号：US10007032B2

公开(公告)日：2018-06-26

申请号：US15159197

申请日：2016-05-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shantao Chen ,  Chienhung Liu

IPC: G03B27/54 ,  G02B3/00 ,  G03F7/20

CPC classification number: G02B3/0006 ,  G02B3/0037 ,  G03F7/70275

Abstract: The present invention discloses an exposure device including: a mask plate, on which a mask pattern is provided; and a first micro lens layer, provided at a light outputting side of the mask plate, wherein the first micro lens layer utilizes light that passes through the mask plate to form a reduced real image of the mask pattern, the real image is located at one side of the first micro lens layer, and the mask plate is located at other side of the first micro lens layer. In the present invention, by utilizing the characteristics of micro lenses, a reduced real image for the mask patter is formed and then projected onto the substrate to be exposed, which effectively increases precision and resolution of exposure and reduces equipment cost and development cost.

公开(公告)号：US11133196B2

公开(公告)日：2021-09-28

申请号：US16303959

申请日：2018-05-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Bin Zhang ,  Chienhung Liu ,  Yucheng Chan ,  Xuefei Sun ,  Tingting Zhou

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/786 ,  H01L21/324 ,  H01L21/02

Abstract: A gate electrode and a method for manufacturing the same, and a method for manufacturing an array substrate are provided. The method for manufacturing a gate electrode may include: providing a substrate, wherein the substrate includes a gate electrode region and a non-gate electrode region; and forming a gate electrode layer on the substrate, wherein the gate electrode layer includes a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region. According to the gate electrode and the method for manufacturing the same, and the method for manufacturing an array substrate, step difference can be eliminated, thereby avoiding an influence of the step difference on the crystallization property of a polysilicon material when an Excimer Laser Annealing (ELA) process is performed on the amorphous silicon layer, and obtaining a better crystallization effect.

公开(公告)号：US09893165B2

公开(公告)日：2018-02-13

申请号：US14905733

申请日：2015-08-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jianbang Huang ,  Yucheng Chan ,  Chienhung Liu

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/266

CPC classification number: H01L29/66492 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/3105 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/78621

Abstract: Embodiments of the present invention disclose a manufacturing method for an array substrate and corresponding manufacturing device, which belong to the technical field of metal oxide semiconductor. The method comprises: forming an active layer, a gate insulating layer and a gate metal layer successively on a substrate; forming a gate pattern with a gate photoresist pattern on the substrate having the gate metal layer; altering a temperature of the gate photoresist pattern, so as to enable the width of the gate photoresist sub-pattern in the gate photoresist pattern to be changed; forming lightly doped drains (LDDs) at two sides of a preset area of the active layer sub-pattern in the active layer of the substrate having the changed gate photoresist pattern, the preset area being a projection area of the gate sub-pattern on the active layer sub-pattern, the length of each of the LDDs being (a−b)/2, wherein a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, b is the width of the gate sub-pattern; stripping the changed gate photoresist pattern. The embodiment of the present invention mitigates or alleviates the problem of relatively low control flexibility and relatively poor feasibility to the LDD length, which improves the control flexibility and feasibility to the LDD length, and can be used for manufacturing an array substrate.

公开(公告)号：US10655947B2

公开(公告)日：2020-05-19

申请号：US16041200

申请日：2018-07-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xuefei Sun ,  Chienhung Liu ,  Zhengliang Li ,  Bin Zhang

IPC: G01B11/06 ,  G01N21/552

Abstract: The present disclosure provides a thickness measuring method and device. The thickness measuring method is used for measuring a thickness of a layer to be measured of a light-transmitting sample to be measured and comprising the steps of: placing the sample to be measured between an optical device and a metal layer, the optical device comprising a light incident surface and a light exit surface; adjusting incident light emitted to the light incident surface of the optical device so that an intensity of light exiting the light exit surface of the optical device is less than 10−12 W/m2, so as to obtain optical parameters of the incident light; and calculating a thickness of the layer to be measured according to the optical parameters of the incident light.

公开(公告)号：US10224252B2

公开(公告)日：2019-03-05

申请号：US15736972

申请日：2017-06-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Bin Zhang ,  Chienhung Liu ,  Yucheng Chan ,  Xuefei Sun ,  Zhanfeng Cao

IPC: H01L21/84 ,  H01L27/146 ,  H01L27/12

Abstract: A method for fabricating an array substrate, an array substrate, and a display device are disclosed. The method includes forming a whole layer of opaque film on a substrate; treating the film to form a transparent region and an opaque region in the film, wherein the opaque region corresponds with a channel region of an active layer; and forming a thin film transistor on the film which has been treated. In the method, prior to forming the thin film transistor, the whole layer of opaque film is formed to comprise the transparent region and the opaque region. When other films are deposited on the whole layer of film, no difference in height occurs, and this further avoids various defects due to difference in height.