Metal-insulator-metal solid-state rectifier
    1.
    发明授权
    Metal-insulator-metal solid-state rectifier 失效
    金属绝缘体 - 金属固态整流器

    公开(公告)号:US3648122A

    公开(公告)日:1972-03-07

    申请号:US3648122D

    申请日:1970-06-19

    CPC classification number: H01L45/00

    Abstract: A metal-insulator-metal layered structure is disclosed which is useful as a rectifier of AC voltage. One of the metal layers is advantageously in the form of a crossgrid-type geometry, in order to afford a large perimeter of contact with the insulator layer. Electrons are injected at the edges of the metal grid through the insulator when the grid goes electrically negative, but not when it goes positive; thereby, rectifying properties are afforded by this metal-insulator-metal structure.

    Abstract translation: 公开了一种可用作交流电压整流器的金属 - 绝缘体 - 金属层状结构。 金属层中的一个有利地是十字网格形状的形式,以便提供与绝缘体层的大的周界。 当电网电气负电时,电子通过绝缘体在金属栅格的边缘注入,而不是当它变为正时; 从而由金属 - 绝缘体 - 金属结构提供整流性能。

    Monolithic semiconductor apparatus adapted for sequential charge transfer
    2.
    发明授权
    Monolithic semiconductor apparatus adapted for sequential charge transfer 失效
    适用于顺序充电转移的单片半导体器件

    公开(公告)号:US3651349A

    公开(公告)日:1972-03-21

    申请号:US3651349D

    申请日:1970-02-16

    Abstract: In monolithic semiconductor devices of the type wherein storage and manipulation of electronic signals representing information are accomplished by the storage and sequential transfer of packets of excess minority carriers localized in artificially induced potential wells, predictable directionality of chargepacket transfer requires that the potential well be asymmetrical, at least during the transfer operation. The instant invention includes the use of overlapping gate electrodes and/or nonuniform dielectric thicknesses under the gate electrodes of MIS structures so that an appropriately asymmetrical potential well always is formed whenever a voltage is applied to any gate electrode.

    Abstract translation: 在这种类型的单片半导体器件中,其中表示信息的电子信号的存储和操纵通过定位在人为诱导的电位阱中的过剩少数载流子的存储和顺序传输而完成,电荷分组传输的可预测的方向性要求潜在的良好 至少在转移操作期间不对称。 本发明包括在MIS结构的栅电极下面使用重叠的栅电极和/或不均匀的介电厚度,使得每当施加电压到任何栅电极时,总是形成适当的非对称势阱。

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