公开(公告)号：US20120014191A1

公开(公告)日：2012-01-19

申请号：US13181404

申请日：2011-07-12

申请人： Azuma SUZUKI ,  Fumihiko TACHIBANA ,  Tomoaki YABE

发明人： Azuma SUZUKI ,  Fumihiko TACHIBANA ,  Tomoaki YABE

IPC分类号： G11C7/00

CPC分类号： G11C11/413

摘要： A semiconductor memory device of an embodiment includes memory cells 2, a write-back determining unit 7, and a read controller 8. Each memory cell 2 is capable of writing and reading through different paths. The write-back determining unit 7 determines whether or not to perform the write-back for a non-selected column, at the time of the write for a selected column. On the basis of the determination result of the write-back determining unit 7, the read controller 8 controls the read of the data used in the write-back for the non-selected column.

摘要翻译： 实施例的半导体存储器件包括存储器单元2，回写确定单元7和读取控制器8.每个存储器单元2能够通过不同的路径进行写入和读取。 回写确定单元7在写入所选择的列时确定是否对未选择的列执行写回。 基于回写确定单元7的确定结果，读取控制器8控制用于非选择列的回写中使用的数据的读取。

公开(公告)号：US20080232148A1

公开(公告)日：2008-09-25

申请号：US12052020

申请日：2008-03-20

申请人： Tomoaki YABE

发明人： Tomoaki YABE

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C15/04 ,  G11C15/046 ,  G11C29/846

摘要： A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal.

摘要翻译： 一种半导体存储器件，包括：第一存储器，其中输入第一地址和第一输入数据，并且将第一输出数据输入到第一地址作为搜索地址输入的内容寻址存储器，并且执行搜索 确定第一地址和缺陷地址是否彼此一致，并且当第一地址和有缺陷地址彼此一致时，输出第二地址和控制信号，第二存​​储器，当第二地址被输入时 输出对应于第二地址的冗余数据，以及多路复用器，当输入控制信号时，将输出数据从第一输出数据切换到冗余数据，并将冗余数据输出到输入/输出端。

公开(公告)号：US20080192527A1

公开(公告)日：2008-08-14

申请号：US12027548

申请日：2008-02-07

申请人： Tomoaki YABE

发明人： Tomoaki YABE

IPC分类号： G11C5/06 ,  G11C11/00 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/412

摘要： A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括第一反相器和第二反相器，连接到第一反相器的输出端的第一存储节点和第二反相器的输入端，以及连接到第一反相器的第二存储节点 第一反相器的输入端子和第二反相器的输出端子，连接到存储单元的字线和分别连接到存储单元的多个位线。 输入数据被写入所选择的存储单元，并且在写入操作中从未选择的存储单元读取的数据被再次写入未选择的存储单元。

公开(公告)号：US20100014375A1

公开(公告)日：2010-01-21

申请号：US12568253

申请日：2009-09-28

申请人： Tomoaki YABE ,  Akihito Tohata

发明人： Tomoaki YABE ,  Akihito Tohata

IPC分类号： G11C5/14 ,  G11C8/08

CPC分类号： G11C8/08 ,  G11C11/413

摘要： A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.

摘要翻译： 半导体存储器件通过使用固定功率和可变功率来工作。 该装置包括多个字线，其选择存储单元阵列的行，多个字线驱动器，每个字线连接到对应的一个字线，并且包括第一CMOS栅极，第一截止开关，其被连接 在固定电源端子和第一CMOS栅极的电源端子之间并在睡眠模式下切断固定功率的开关电路，连接到多个字线并将多个字线连接到接地端子的开关电路 睡眠模式和通过使用固定功率产生可变功率并在睡眠模式下将可变功率设置为0V的功率控制电路。

公开(公告)号：US20080137393A1

公开(公告)日：2008-06-12

申请号：US11952441

申请日：2007-12-07

申请人： Gou FUKANO ,  Tomoaki YABE ,  Nobuaki OTSUKA

发明人： Gou FUKANO ,  Tomoaki YABE ,  Nobuaki OTSUKA

IPC分类号： G11C5/06 ,  G11C5/02

CPC分类号： G11C7/18

摘要： This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

摘要翻译： 该半导体存储器件包括具有以矩阵形式布置的多个存储单元的多个子阵列。 每个本地位线连接到在子阵列中沿列方向布置的多个存储单元。 另外，全局位线连接到多个局部位线。 列解码器连接到全局位线。 全局位线从列解码器向多个子阵列延伸，并且在与该列解码器最远的区域中形成的最远子阵列之前被切割。