公开(公告)号：US20100134182A1

公开(公告)日：2010-06-03

申请号：US12701896

申请日：2010-02-08

Applicant: Ashok Kumar KAPOOR ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kumar KAPOOR ,  Robert Strain ,  Reuven Marko

IPC: G05F3/02 ,  H01L21/8238

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract translation: 公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。 根据本发明的装置可在低于2V的电压下工作。 这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。 使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。 该方案控制每个晶体管的阈值电压。 在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。 在ON状态下，阈值电压的大小减小，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

公开(公告)号：US08048732B2

公开(公告)日：2011-11-01

申请号：US12701896

申请日：2010-02-08

Applicant: Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H01L21/8238

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract translation: 公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。 根据本发明的装置可在低于2V的电压下工作。 这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。 使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。 该方案控制每个晶体管的阈值电压。 在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。 在ON状态下，阈值电压的大小减小，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

公开(公告)号：US07898297B2

公开(公告)日：2011-03-01

申请号：US11684466

申请日：2007-03-09

Applicant: Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H03K19/096

CPC classification number: H03K19/0963 ,  H01L21/823807 ,  H01L27/0727 ,  H01L27/0921

Abstract: Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a change to existing MOS technology processes. Threshold voltage of the transistor is controlled, such that in the Off state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. The advantages provided by apply to dynamic logic, as well as in the specific well separation imposed by design rules because well potential difference are lower than the supply voltage swing.

Abstract translation: 可在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管，其面积效率高，并且表现出改进的驱动强度和漏电流。 使用动态阈值电压控制方案，其不需要改变现有的MOS技术过程。 控制晶体管的阈值电压，使得在关断状态下，晶体管的阈值电压被设置为高，从而将晶体管泄漏保持在较小的值。 动态逻辑提供的优点，以及设计规则施加的具体井分离，因为潜在电位差低于电源电压摆幅。

公开(公告)号：US07683433B2

公开(公告)日：2010-03-23

申请号：US11533332

申请日：2006-09-19

Applicant: Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract translation: 公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。 根据本发明的装置可在低于2V的电压下工作。 这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。 使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。 该方案控制每个晶体管的阈值电压。 在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。 在ON状态下，阈值电压的大小减小，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

公开(公告)号：US08247840B2

公开(公告)日：2012-08-21

申请号：US12348797

申请日：2009-01-05

Applicant: Ashok Kumar Kapoor ,  Robert Strain

Inventor： Ashok Kumar Kapoor ,  Robert Strain

IPC: H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/66636 ,  H01L29/7833 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Abstract translation: 使用正向偏置二极管来减少在绝缘体上硅（SOI）上实现的晶体管的泄漏电流是一个特别的挑战，因为难以实现与晶体管栅极之下的区域的有效接触。 通过与晶体管外部的区域接触的隧道在源极下方的SOI栅极指中的改进的实现。 另一实施例使用漏极延伸植入物来提供良好的通道连接。

公开(公告)号：US20090174464A1

公开(公告)日：2009-07-09

申请号：US12348797

申请日：2009-01-05

Applicant: Ashok Kumar Kapoor ,  Robert Strain

Inventor： Ashok Kumar Kapoor ,  Robert Strain

IPC: H03K3/01 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/66636 ,  H01L29/7833 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Abstract translation: 使用正向偏置二极管来减少在绝缘体上硅（SOI）上实现的晶体管的泄漏电流是一个特别的挑战，因为难以实现与晶体管栅极之下的区域的有效接触。 通过与晶体管外部的区域接触的隧道在源极下方的SOI栅极指中的改进的实现。 另一实施例使用漏极延伸植入物来提供良好的通道连接。

公开(公告)号：US20070229145A1

公开(公告)日：2007-10-04

申请号：US11684466

申请日：2007-03-09

Applicant: Ashok Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H03K3/01

CPC classification number: H03K19/0963 ,  H01L21/823807 ,  H01L27/0727 ,  H01L27/0921

Abstract: Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a change to existing MOS technology processes. Threshold voltage of the transistor is controlled, such that in the Off state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. The advantages provided by apply to dynamic logic, as well as in the specific well separation imposed by design rules because well potential difference are lower than the supply voltage swing.

Abstract translation: 可在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管，其面积效率高，并且表现出改进的驱动强度和漏电流。 使用动态阈值电压控制方案，其不需要改变现有的MOS技术过程。 控制晶体管的阈值电压，使得在关断状态下，晶体管的阈值电压被设置为高，从而将晶体管泄漏保持在较小的值。 动态逻辑提供的优点，以及设计规则施加的具体井分离，因为潜在电位差低于电源电压摆幅。

公开(公告)号：US20070069306A1

公开(公告)日：2007-03-29

申请号：US11533332

申请日：2006-09-19

Applicant: Ashok Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H01L29/94

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract translation: 公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。 根据本发明的装置可在低于2V的电压下工作。 这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。 使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。 该方案控制每个晶体管的阈值电压。 在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。 在ON状态下，阈值电压的大小减小，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

公开(公告)号：US07863689B2

公开(公告)日：2011-01-04

申请号：US12348809

申请日：2009-01-05

Applicant: Robert Strain

Inventor： Robert Strain

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.

Abstract translation: 在非接地井上实现的MOS晶体管的深亚微米阱具有两种工作模式：电流吸收模式和电流源模式。 当作为电流吸收器的操作被很好地理解并成功地控制时，还需要控制在井的当前源模式中提供的电流。 肖特基二极管连接在阱和栅极之间，肖特基二极管的栅极高度高于源阱的PN结的势垒高度。 对于NMOS晶体管，当栅极为高电平时，电流流过PN结。 当栅极低时，电流流过肖特基二极管。 电流的这种差异导致晶体管阈值的差异，从而当在当前源模式下工作时，使用来自阱的电流实现动态阈值电压。

公开(公告)号：US20090206380A1

公开(公告)日：2009-08-20

申请号：US12348809

申请日：2009-01-05

Applicant: Robert Strain

Inventor： Robert Strain

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.

Abstract translation: 在非接地井上实现的MOS晶体管的深亚微米阱具有两种工作模式：电流吸收模式和电流源模式。 当作为电流吸收器的操作被很好地理解并成功地控制时，还需要控制在井的当前源模式中提供的电流。 肖特基二极管连接在阱和栅极之间，肖特基二极管的栅极高度高于源阱的PN结的势垒高度。 对于NMOS晶体管，当栅极为高电平时，电流流过PN结。 当栅极低时，电流流过肖特基二极管。 电流的这种差异导致晶体管阈值的差异，从而当在当前源模式下工作时，使用来自阱的电流实现动态阈值电压。