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公开(公告)号：US20190056955A1
公开(公告)日：2019-02-21
申请号：US16047336
申请日：2018-07-27
Applicant: Arm Limited
Inventor： Jussi Tuomas Pennala , Robert John Rees , Hakan Lars-Goran Persson
Abstract: A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.
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公开(公告)号：US20210126736A1
公开(公告)日：2021-04-29
申请号：US17078047
申请日：2020-10-22
Applicant: Arm Limited
Inventor： Sven Ola Johannes Hugosson , Jakob Axel Fries , Hakan Lars-Goran Persson , Muhammad Ali Shami
IPC: H04L1/00 , H04L12/741
Abstract: When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.
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公开(公告)号：US11515961B2
公开(公告)日：2022-11-29
申请号：US17078047
申请日：2020-10-22
Applicant: Arm Limited
Inventor： Sven Ola Johannes Hugosson , Jakob Axel Fries , Hakan Lars-Goran Persson , Muhammad Ali Shami
Abstract: When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.
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公开(公告)号：US20210294535A1
公开(公告)日：2021-09-23
申请号：US16823044
申请日：2020-03-18
Applicant: Arm Limited
Inventor： Jian Wang , Hakan Lars-Goran Persson
IPC: G06F3/06 , H04N19/182 , H04N19/88
Abstract: When operating a data processing system comprising a data encoder operable to perform a first encoding scheme that is configured for processing sets of data arranged in a first data format, for a plurality of sets of data received in a second, different data format, the bits for at least some of the received plurality of sets of data in the second data format are re-ordered to map the bits for the at least some of the received plurality of sets of data in the second data format into the first arrangement of bits associated with the first data format to thereby generate from the received plurality of sets of data in the second data format one or more sets of data in the first data format for processing using the first encoding scheme.
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公开(公告)号：US10861125B2
公开(公告)日：2020-12-08
申请号：US16402031
申请日：2019-05-02
Applicant: Arm Limited
Inventor： Arne Aas , Sandeep Kakarlapudi , Hakan Lars-Goran Persson
Abstract: When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.
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Patent Agency Ranking
公开(公告)号：US20200065107A1
公开(公告)日：2020-02-27
申请号：US16112094
申请日：2018-08-24
Applicant: Arm Limited
Inventor： Mark Underwood , Hakan Lars-Goran Persson
Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by a command stream execution unit of the accelerator. A pre-execution unit is provided that is operable to interpret commands fetched from command stream storage before the command is provided to the command stream execution unit for implementation to determine whether the pre-execution unit is able to perform an action in response to the command and, when the pre-execution unit is able to do so, to perform an action in response to the command.
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公开(公告)号：US10824467B2
公开(公告)日：2020-11-03
申请号：US16056927
申请日：2018-08-07
Applicant: Arm Limited
Inventor： Mark Underwood , Hakan Lars-Goran Persson
Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by the accelerator. When a request for processing includes protected content, the host processor includes within a command for a command stream, an indication that a subsequent sequence of one or more command(s) within that command stream associated with the protected content is to be implemented by the accelerator in a protected mode of operation. Then, when that command is executed, the accelerator initiates or requests a switch into the protected mode of operation.
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公开(公告)号：US10732978B2
公开(公告)日：2020-08-04
申请号：US16112094
申请日：2018-08-24
Applicant: Arm Limited
Inventor： Mark Underwood , Hakan Lars-Goran Persson
Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by a command stream execution unit of the accelerator. A pre-execution unit is provided that is operable to interpret commands fetched from command stream storage before the command is provided to the command stream execution unit for implementation to determine whether the pre-execution unit is able to perform an action in response to the command and, when the pre-execution unit is able to do so, to perform an action in response to the command.
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公开(公告)号：US20200065095A1
公开(公告)日：2020-02-27
申请号：US16107250
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Mark Underwood , Hakan Lars-Goran Persson , Arne Aas
Abstract: When executing a program on a data processor comprising an execution unit for executing instructions in a program to be executed by the data processor, the execution unit being associated with one or more hardware units operable to execute instructions, at least one instruction in a program is associated with an indication of whether the instruction should be issued directly for execution by a hardware unit or should be intercepted during its execution by the execution unit. The execution unit then, when decoding the instruction for execution by a hardware unit in the program, determines from the indication associated with the instruction whether the instruction should be issued directly for execution by a hardware unit or intercepted during its execution by the execution unit, and issues the instruction for execution by a hardware unit directly, or pauses execution of the instruction and performs another operation, accordingly.
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公开(公告)号：US10475147B2
公开(公告)日：2019-11-12
申请号：US15428645
申请日：2017-02-09
Applicant: Arm Limited
Abstract: A graphics processing system comprises a pair of graphics processing units that are connected to each other via communications bridges that can allow communication between the connected graphics processing units. One of the graphics processing units is operable to act as a master graphics processing unit controlling graphics processing operations on the other graphics processing unit which is operable as a slave graphics processing unit to perform graphics processing operations under the control of the master graphics processing unit. Each graphics processing unit of the pair of graphics processing units is also capable of operating in a standalone mode, in which the graphics processing unit operates independently of the other graphics processing unit to perform a graphics processing task.
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