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    Non-volatile memory-based compact mixed-signal multiply-accumulate engine
    1.
    发明授权
    Non-volatile memory-based compact mixed-signal multiply-accumulate engine 有权

    公开(公告)号：US11886987B2

    公开(公告)日：2024-01-30

    申请号：US16451205

    申请日：2019-06-25

    Applicant: Arm Limited

    Inventor： Shidhartha Das ,  Matthew Mattina ,  Glen Arnold Rosendale ,  Fernando Garcia Redondo

    IPC: G06N3/065 ,  G06N3/04 ,  G06N3/08

    CPC classification number: G06N3/065 ,  G06N3/04 ,  G06N3/08

    Abstract: A multiply-accumulate method and architecture are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally modulates the equivalent conductance of individual networks among the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network. A first partial selection of weights within the neural network is mapped into the equivalent conductances of the networks in the columns to enable the computation of multiply-and-accumulate operations by mixed-signal computation. The logic updates the mappings to select a second partial selection of weights to compute additional multiply-and-accumulate operations and repeats the mapping and computation operations until all computations for the neural network are completed.

    Refactoring mac operations
    3.
    发明授权
    Refactoring mac operations 有权

    公开(公告)号：US11922169B2

    公开(公告)日：2024-03-05

    申请号：US17674503

    申请日：2022-02-17

    Applicant: Arm Limited

    Inventor： Matthew Mattina ,  Shidhartha Das ,  Glen Arnold Rosendale ,  Fernando Garcia Redondo

    IPC: G06F9/38 ,  G06F7/487 ,  G06F7/544 ,  G06F9/30 ,  G06F17/16 ,  G06N3/06

    CPC classification number: G06F9/3893 ,  G06F7/4876 ,  G06F7/5443 ,  G06F9/30014 ,  G06F17/16 ,  G06N3/06

    Abstract: A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.

    Non-Volatile Memory Accelerator for Artificial Neural Networks
    7.
    发明申请
    Non-Volatile Memory Accelerator for Artificial Neural Networks 有权

    公开(公告)号：US20220101085A1

    公开(公告)日：2022-03-31

    申请号：US17036490

    申请日：2020-09-29

    Applicant: Arm Limited

    Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Paul Nicholas Whatmough ,  Glen Arnold Rosendale

    IPC: G06N3/04 ,  G11C13/00 ,  G06F7/544

    Abstract: A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.

    Devices and Methods for Controlling Write Operations
    8.
    发明申请
    Devices and Methods for Controlling Write Operations 有权

    公开(公告)号：US20210090653A1

    公开(公告)日：2021-03-25

    申请号：US16582743

    申请日：2019-09-25

    Applicant: Arm Limited

    Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Glen Arnold Rosendale ,  George McNeil Lattimore ,  Mudit Bhargava

    IPC: G11C13/00

    Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

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