公开(公告)号：US20240330671A1

公开(公告)日：2024-10-03

申请号：US18128496

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Rahul Reddy KOMATIREDDI ,  Rohith CHERIKKALLIL ,  Sneha Rupa KONGARA ,  Sachin DANGAYACH ,  Prayudi LIANTO ,  Peng SUO ,  Krishnaprasad Reddy MALLAVARAM ,  Satwik Swarup MISHRA ,  Si En CHAN ,  Remus Zhen Hui KOH ,  Khor Wui CHENG ,  Yin Wei LIM

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: A method and apparatus for training a learning model for the automatic detection and classification of defects on wafers includes receiving labeled images of wafer defects having multiple defect classifications, creating a first training set including the received labeled images of wafer defects, training the machine learning model to automatically detect and classify wafer defects in a first stage using the first training set, blending at least one set of at least two labeled images having different classifications to generate additional labeled image data, creating a second training set including the blended, additional labeled image data, and training the machine learning model to automatically detect and classify wafer defects in a second stage using the second training set. The trained machine learning model can then be applied to at least one unlabeled wafer image to determine at least one defect classification for the at least one unlabeled wafer image.

公开(公告)号：US20240331126A1

公开(公告)日：2024-10-03

申请号：US18128487

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Rahul Reddy KOMATIREDDI ,  Rohith CHERIKKALLIL ,  Sneha Rupa KONGARA ,  Satwik Swarup MISHRA ,  Sachin DANGAYACH ,  Si En CHAN ,  Remus Zhen Hui KOH ,  Prayudi LIANTO ,  Yin Wei LIM ,  Peng SUO ,  Krishnaprasad Reddy MALLAVARAM ,  Khor Wui CHENG

IPC: G06T7/00 ,  G06V10/764 ,  G06V10/82

CPC classification number: G06T7/0004 ,  G06V10/764 ,  G06V10/82 ,  G06T2207/30148

Abstract: A method and apparatus for training a learning model for automatic defect detection and classification of at least a portion of a processed wafer include receiving labeled images having defect classification types and features for portions of a post-processed wafer, creating a first training set comprising the received labeled images, training the machine learning model to automatically classify wafer portions based on at least one detected defect in respective wafer portions using the first training set, receiving labeled wafer profiles having respective downstream yield data, creating a second training set comprising the labeled wafer profiles and training the machine learning model, using the second training set, to automatically determine a respective downstream yield of a wafer based on a respective wafer profile. The machine learning model can be applied to at least one unlabeled wafer image to determine at least one defect classification for at least one portion of a wafer.

公开(公告)号：US20240331131A1

公开(公告)日：2024-10-03

申请号：US18128491

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Rahul Reddy KOMATIREDDI ,  Rohith CHERIKKALLIL ,  Sneha Rupa KONGARA ,  Satwik Swarup MISHRA ,  Sachin DANGAYACH ,  Si En CHAN ,  Remus Zhen Hui KOH ,  Prayudi LIANTO ,  Yin Wei LIM ,  Peng SUO ,  Krishnaprasad Reddy MALLAVARAM ,  Khor Wui CHENG

IPC: G06T7/00 ,  G06T7/13

CPC classification number: G06T7/001 ,  G06T7/13 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148

Abstract: A method, apparatus and system for the automatic detection and measurement of chipping defects on diced wafers includes receiving an image of at least a portion of a diced wafer, aligning the received image of the at least the portion of the diced wafer, determining edges of the at least the portion of the diced wafer depicted in the aligned, received image, automatically determining at least one baseline from which to measure chipping defects on the at least the portion of the diced wafer from the determined edges, and measuring chipping defects on the at least the portion of the diced wafer using at least one determined, respective baseline. In some embodiments, the method, apparatus and system can further include applying a machine learning model to measured chipping defects to determine if a critical failure exists on the diced wafer.

公开(公告)号：US20220328354A1

公开(公告)日：2022-10-13

申请号：US17847419

申请日：2022-06-23

Applicant: Applied Materials, Inc.

Inventor： Peng SUO ,  Ying W. WANG ,  Guan Huei SEE ,  Chang Bum YONG ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/288 ,  H01L21/285 ,  H01L21/306

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

公开(公告)号：US20240110284A1

公开(公告)日：2024-04-04

申请号：US18372792

申请日：2023-09-26

Applicant: Applied Materials, Inc.

Inventor： Lulu XIONG ,  Kevin Hsiao ,  Chris LIU ,  Chieh-Wen LO ,  Sean M. SEUTTER ,  Deenesh PADHI ,  Prayudi LIANTO ,  Peng SUO ,  Guan Huei SEE ,  Zongbin WANG ,  Shengwei ZENG ,  Balamurugan RAMASAMY

IPC: C23C16/505 ,  C23C16/04 ,  C23C16/32 ,  C23C16/56 ,  H01J37/32

CPC classification number: C23C16/505 ,  C23C16/045 ,  C23C16/325 ,  C23C16/56 ,  H01J37/32165 ,  H01J37/3244 ,  H01J2237/3321

Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.

公开(公告)号：US20240087958A1

公开(公告)日：2024-03-14

申请号：US18508801

申请日：2023-11-14

Applicant: Applied Materials, Inc.

Inventor： Peng SUO ,  Ying W. WANG ,  Guan Huei SEE ,  Chang Bum YONG ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/288 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/76898 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/30625 ,  H01L21/308

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

公开(公告)号：US20220165621A1

公开(公告)日：2022-05-26

申请号：US16953869

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Peng SUO ,  Ying W. WANG ,  Guan Huei SEE ,  Chang Bum YONG ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/306 ,  H01L21/285 ,  H01L21/288

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.