Invention Application
- Patent Title: METHODS OF FORMING THROUGH-SILICON VIAS IN SUBSTRATES FOR ADVANCED PACKAGING
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Application No.: US16953869Application Date: 2020-11-20
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Publication No.: US20220165621A1Publication Date: 2022-05-26
- Inventor: Peng SUO , Ying W. WANG , Guan Huei SEE , Chang Bum YONG , Arvind SUNDARRAJAN
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/308 ; H01L21/306 ; H01L21/285 ; H01L21/288
Abstract:
The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.
Information query
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