公开(公告)号：US20220336222A1

公开(公告)日：2022-10-20

申请号：US17244873

申请日：2021-04-29

Applicant: Applied Materials, Inc.

Inventor： Hailong ZHOU ,  Sean KANG ,  Kenji TAKESHITA ,  Rajinder DHINDSA ,  Taehwan LEE ,  Iljo KWAK

IPC: H01L21/311

Abstract: Embodiments of this disclosure include a method of processing a substrate that includes etching a first dielectric material formed on a substrate that is disposed on a substrate supporting surface of a substrate support assembly disposed within a processing region of a plasma processing chamber. The etching process may include delivering a process gas to the processing region, wherein the process gas comprises a first fluorocarbon containing gas and a first process gas, delivering, by use of a radio frequency generator, a radio frequency signal to a first electrode to form a plasma in the processing region, and establishing, by use of a first pulsed-voltage waveform generator, a first pulsed voltage waveform at a biasing electrode disposed within the substrate support assembly. The first pulsed voltage waveform comprises a series of repeating pulsed waveform cycles that each include a first portion that occurs during a first time interval, a second portion that occurs during a second time interval, and a peak-to-peak voltage. The pulsed voltage waveform is substantially constant during at least a portion of the second time interval.

公开(公告)号：US20250149337A1

公开(公告)日：2025-05-08

申请号：US18913143

申请日：2024-10-11

Applicant: Applied Materials, Inc.

Inventor： Jing ZHANG ,  Gene LEE ,  Kenji TAKESHITA ,  Anatoli CHLENOV

IPC: H01L21/033

Abstract: A method of selectively etching a hardmask layer formed on a device substrate. The method includes supplying an etching gas mixture to a process region of a processing chamber, where a device substrate is disposed in the process region when the etching gas mixture is supplied to the process region, where the device substrate may include a substrate, at least one cavity formed in the substrate, and a hardmask layer formed over the at least one cavity and over the substrate. The method also includes providing radio frequency (rf) power to the etching gas mixture to form a plasma in the process region.

公开(公告)号：US20230223268A1

公开(公告)日：2023-07-13

申请号：US17572397

申请日：2022-01-10

Applicant: Applied Materials, Inc.

Inventor： Sean KANG ,  Olivier LUERE ,  Kenji TAKESHITA ,  Sanghyuk CHOI ,  Mengnan ZOU ,  Zihao DING

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/02126 ,  H01L21/31116

Abstract: Embodiments of the present disclosure generally relate to a method for etching a film stack with high selectivity and low etch recipe transition periods. In one embodiment, a method for etching a film stack having stacked pairs of oxide and nitride layers is described. The method includes transferring a substrate having a film stack formed thereon into a processing chamber, providing a first bias voltage to the substrate, etching an oxide layer of the film stack while providing the first bias voltage to the substrate, providing a second bias voltage to the substrate, the second bias voltage greater than the first bias voltage, and etching a nitride layer of the film stack while providing the second bias voltage to the substrate.

公开(公告)号：US20230402286A1

公开(公告)日：2023-12-14

申请号：US17837958

申请日：2022-06-10

Applicant: Applied Materials, Inc.

Inventor： Daisuke SHIMIZU ,  Li LING ,  Hikaru WATANABE ,  Kenji TAKESHITA

IPC: H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/3065 ,  H01J37/32128 ,  H01J37/32146 ,  H01J37/32449 ,  H01J2237/334

Abstract: Methods and apparatus for etching a substrate in a plasma etch chamber are provided. In one example, the method includes exposing a substrate disposed on a substrate supporting surface of a substrate support to a plasma within a processing chamber, and applying a voltage waveform to an electrode disposed in the substrate support while the substrate is exposed to the plasma during a plurality of macro etch cycles. Each macro etch cycle includes a first macro etch period and a second macro etch period. The macro etch period includes a plurality of micro etch cycles. Each micro etch cycle has a bias power on (BPON) period and a bias power off (BPOFF) period, wherein a duration of the BPON period being less than a duration of the BPOFF period. Bias power is predominantly not applied to the electrode during the second macro etch period.