公开(公告)号：US10911267B1

公开(公告)日：2021-02-02

申请号：US16845865

申请日：2020-04-10

Applicant: Apple Inc.

Inventor： Luca O. Iuliano ,  Doron Rajwan ,  Ali Rabbani Rankouhi

IPC: H04L25/02 ,  H04L1/00 ,  H04L25/49

Abstract: An apparatus includes an encoding circuit, and a communication bus having conductive traces configured to transfer a data payload, including a control signal and up to a maximum number of data words. The encoding circuit is configured to receive an uncompressed data payload and a mask value, and to create, using the mask value, the control signal, the control signal indicative of whether the uncompressed data payload includes one or more non-enabled data words. In response to a determination that the control signal indicates that the uncompressed data payload includes one or more non-enabled data words, the encoding circuit is configured to create a compressed data payload from the uncompressed data payload, and to send, to a decoding circuit, the compressed data payload and the control signal via the plurality of conductive traces of the communication bus. The compressed data payload includes the mask value.

公开(公告)号：US11303478B2

公开(公告)日：2022-04-12

申请号：US17164482

申请日：2021-02-01

Applicant: Apple Inc.

Inventor： Luca O. Iuliano ,  Doron Rajwan ,  Ali Rabbani Rankouhi

IPC: H04L25/02 ,  H04L1/00 ,  H04L25/49

Abstract: An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.

公开(公告)号：US20210320826A1

公开(公告)日：2021-10-14

申请号：US17164482

申请日：2021-02-01

Applicant: Apple Inc.

Inventor： Luca O. Iuliano ,  Doron Rajwan ,  Ali Rabbani Rankouhi

IPC: H04L25/02 ,  H04L1/00 ,  H04L25/49

Abstract: An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.

公开(公告)号：US20250095274A1

公开(公告)日：2025-03-20

申请号：US18524265

申请日：2023-11-30

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Luca O. Iuliano ,  David J. Bermingham ,  Christopher A. Burns

IPC: G06T15/06 ,  G06T1/20 ,  G06T17/00

Abstract: Techniques are disclosed relating to graphics processors that support ray tracing. In disclosed embodiments, ray intersect circuitry is configured to access a traversal stack used for traversal of multiple levels of a bounding volume hierarchy (BVH) acceleration data structure (ADS) according to a depth-first search to retrieve: coordinates of a first bounding region for a child node and a local ray parameter value that indicates a point along a ray at which an intersection with a second bounding region for the child node's parent node was detected. The accelerator circuitry may compare the local ray parameter value with an end ray parameter value to determine whether to traverse to the child node as part of traversal of the BVH.

公开(公告)号：US20250095098A1

公开(公告)日：2025-03-20

申请号：US18524729

申请日：2023-11-30

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Roman Tereshin ,  Luca O. Iuliano ,  Sheenam Jayaswal ,  Rohit Kumar Singh

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06T15/00

Abstract: Techniques are disclosed relating to graphics processor that support ray tracing. In particular, shader circuitry may be configured to adjust a scheduling priority of a single-instruction multiple-data (SIMD) group of a shader program based on a hint that the SIMD group has an upcoming ray intersect command for ray intersect accelerator circuitry and based on a resource usage indication from the ray intersect accelerator circuitry. This may advantageously reduce cache thrashing, e.g., when shaders may allocate memory for ray intersect commands and fill a shared cache faster than the ray intersect accelerator circuitry can process the rays.