公开(公告)号：US11443479B1

公开(公告)日：2022-09-13

申请号：US17324857

申请日：2021-05-19

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Leela Kishore Kothamasu ,  Zelin Zhang ,  Guanlan Xu ,  Eddie M. Robinson

IPC: G06F13/362 ,  G06T15/83 ,  G06T15/04 ,  G06T15/00 ,  G06F13/16

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

公开(公告)号：US20250104181A1

公开(公告)日：2025-03-27

申请号：US18795437

申请日：2024-08-06

Applicant: Apple Inc.

Inventor： Karthik Ramani ,  Tyson J. Bergland ,  Leela Kishore Kothamasu ,  Hongzhou Zhao ,  Winnie W. Yeung ,  Mladen Wilder

IPC: G06T1/60 ,  G06F12/0891 ,  G06T15/00

Abstract: Techniques are disclosed relating to data compression in graphics processors. In some embodiments, cache circuitry is coupled to shader processor circuitry and is configured to store graphics data that includes a compressed block of data associated with a surface and metadata for the compressed block of data. Metadata coherence circuitry may cache the metadata for the compressed block of data, receive an indication of a write command for non-compressed data associated with the surface, wherein the write command identifies the metadata and has a different address than the compressed block of data, and determine, based on the metadata and the indication, to invalidate the compressed block of data in the cache circuitry. This may maintain read/write coherence in a cache that stores both compressed and uncompressed data, in some embodiments.

公开(公告)号：US20220375161A1

公开(公告)日：2022-11-24

申请号：US17816632

申请日：2022-08-01

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Leela Kishore Kothamasu ,  Zelin Zhang ,  Guanlan Xu ,  Eddie M. Robinson

IPC: G06T15/83 ,  G06F13/362 ,  G06T15/00 ,  G06T15/04 ,  G06F13/16

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

公开(公告)号：US20250103493A1

公开(公告)日：2025-03-27

申请号：US18410413

申请日：2024-01-11

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Zelin Zhang ,  Cheng Li ,  Hungse Cha ,  Leela Kishore Kothamasu

IPC: G06F12/0811 ,  G06F12/12

Abstract: Techniques are disclosed relating to graphics processor data caches. In some embodiments, datapath executes instructions that operate on input operands from architectural registers. Data cache circuitry caches architectural register data for the datapath circuitry. Scoreboard circuitry tracks, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry and a pointer to the entry of the data cache circuitry. Tiered scoreboard circuitry and data storage circuitry may be implemented (e.g., to provide fast scoreboard access for active threads and to give a landing spot for long-latency data retrieval operations). Various disclosed techniques may improve cache performance, reduce power consumption, reduce area, or some combination thereof.

公开(公告)号：US11842436B2

公开(公告)日：2023-12-12

申请号：US17816632

申请日：2022-08-01

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Leela Kishore Kothamasu ,  Zelin Zhang ,  Guanlan Xu ,  Eddie M. Robinson

IPC: G06F13/362 ,  G06T15/83 ,  G06T15/04 ,  G06T15/00 ,  G06F13/16

CPC classification number: G06T15/83 ,  G06F13/1668 ,  G06F13/3625 ,  G06T15/005 ,  G06T15/04

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.