公开(公告)号：US20250104181A1

公开(公告)日：2025-03-27

申请号：US18795437

申请日：2024-08-06

Applicant: Apple Inc.

Inventor： Karthik Ramani ,  Tyson J. Bergland ,  Leela Kishore Kothamasu ,  Hongzhou Zhao ,  Winnie W. Yeung ,  Mladen Wilder

IPC: G06T1/60 ,  G06F12/0891 ,  G06T15/00

Abstract: Techniques are disclosed relating to data compression in graphics processors. In some embodiments, cache circuitry is coupled to shader processor circuitry and is configured to store graphics data that includes a compressed block of data associated with a surface and metadata for the compressed block of data. Metadata coherence circuitry may cache the metadata for the compressed block of data, receive an indication of a write command for non-compressed data associated with the surface, wherein the write command identifies the metadata and has a different address than the compressed block of data, and determine, based on the metadata and the indication, to invalidate the compressed block of data in the cache circuitry. This may maintain read/write coherence in a cache that stores both compressed and uncompressed data, in some embodiments.