知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.038 seconds)

    Scoreboard for Register Data Cache
    1.
    发明申请
    Scoreboard for Register Data Cache 有权

    公开(公告)号：US20250103493A1

    公开(公告)日：2025-03-27

    申请号：US18410413

    申请日：2024-01-11

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Zelin Zhang ,  Cheng Li ,  Hungse Cha ,  Leela Kishore Kothamasu

    IPC: G06F12/0811 ,  G06F12/12

    Abstract: Techniques are disclosed relating to graphics processor data caches. In some embodiments, datapath executes instructions that operate on input operands from architectural registers. Data cache circuitry caches architectural register data for the datapath circuitry. Scoreboard circuitry tracks, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry and a pointer to the entry of the data cache circuitry. Tiered scoreboard circuitry and data storage circuitry may be implemented (e.g., to provide fast scoreboard access for active threads and to give a landing spot for long-latency data retrieval operations). Various disclosed techniques may improve cache performance, reduce power consumption, reduce area, or some combination thereof.

    Snapshot arbitration techniques for memory requests
    2.
    发明授权
    Snapshot arbitration techniques for memory requests 有权

    公开(公告)号：US11842436B2

    公开(公告)日：2023-12-12

    申请号：US17816632

    申请日：2022-08-01

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Leela Kishore Kothamasu ,  Zelin Zhang ,  Guanlan Xu ,  Eddie M. Robinson

    IPC: G06F13/362 ,  G06T15/83 ,  G06T15/04 ,  G06T15/00 ,  G06F13/16

    CPC classification number: G06T15/83 ,  G06F13/1668 ,  G06F13/3625 ,  G06T15/005 ,  G06T15/04

    Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

    Compression techniques and hierarchical caching
    3.
    发明授权
    Compression techniques and hierarchical caching 有权

    公开(公告)号：US11488350B2

    公开(公告)日：2022-11-01

    申请号：US17338846

    申请日：2021-06-04

    Applicant: Apple Inc.

    Inventor： Anthony P. DeLaurier ,  Karl D. Mann ,  Tyson J. Bergland ,  Winnie W. Yeung

    IPC: G06T15/80 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36

    Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

    Cache Control to Preserve Register Data
    4.
    发明申请
    Cache Control to Preserve Register Data 有权

    公开(公告)号：US20250094357A1

    公开(公告)日：2025-03-20

    申请号：US18962158

    申请日：2024-11-27

    Applicant: Apple Inc.

    Inventor： Jonathan M. Redshaw ,  Winnie W. Yeung ,  Benjiman L. Goodman ,  David K. Li ,  Zelin Zhang ,  Yoong Chert Foo

    IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/0891

    Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

    Cache arbitration for address translation requests
    5.
    发明授权
    Cache arbitration for address translation requests 有权

    公开(公告)号：US11467959B1

    公开(公告)日：2022-10-11

    申请号：US17324824

    申请日：2021-05-19

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Cheng Li

    IPC: G06F12/0802 ,  G06F12/1027

    Abstract: Techniques are disclosed relating to caching for address translation. In some embodiments, address translation circuitry is configured to process requests to translate addresses in a first address space to addresses in a second address space. The translation circuitry may include cache circuitry configured to store translation information, arbitration circuitry configured to arbitrate among ready requests for access to entries of the cache, and hazard circuitry. The hazard circuitry may assign a first request to an ready status the arbitration circuitry based on detection of an absence of hazards for a first address of the first request and add a second request to a queue of requests for the arbitration circuitry based on detection of a hazard for a second address of the second request. Independent arbitration for requests without hazards may improve performance in various aspects, relative to traditional techniques.

    Multi-block cache fetch techniques
    7.
    发明授权
    Multi-block cache fetch techniques 有权

    公开(公告)号：US12248399B2

    公开(公告)日：2025-03-11

    申请号：US17324800

    申请日：2021-05-19

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Cheng Li

    IPC: G06F12/0811 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/0891 ,  G06F13/16

    Abstract: Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

    Cache control to preserve register data
    8.
    发明授权
    Cache control to preserve register data 有权

    公开(公告)号：US12182037B2

    公开(公告)日：2024-12-31

    申请号：US18173500

    申请日：2023-02-23

    Applicant: Apple Inc.

    Inventor： Jonathan M. Redshaw ,  Winnie W. Yeung ,  Benjiman L. Goodman ,  David K. Li ,  Zelin Zhang ,  Yoong Chert Foo

    IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/0891

    Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

    Compression Techniques and Hierarchical Caching
    9.
    发明申请
    Compression Techniques and Hierarchical Caching 有权

    公开(公告)号：US20210295593A1

    公开(公告)日：2021-09-23

    申请号：US17338846

    申请日：2021-06-04

    Applicant: Apple Inc.

    Inventor： Anthony P. DeLaurier ,  Karl D. Mann ,  Tyson J. Bergland ,  Winnie W. Yeung

    IPC: G06T15/80 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36

    Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

Patent Agency Ranking