公开(公告)号：US20240005972A1

公开(公告)日：2024-01-04

申请号：US18346565

申请日：2023-07-03

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C7/22 ,  H03M1/82 ,  G11C7/10

CPC classification number: G11C7/222 ,  H03M1/82 ,  G11C7/1087 ,  G11C7/106

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US11694733B2

公开(公告)日：2023-07-04

申请号：US17406817

申请日：2021-08-19

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C8/00 ,  G11C7/22 ,  H03M1/82 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1087 ,  H03M1/82

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US20230059200A1

公开(公告)日：2023-02-23

申请号：US17406817

申请日：2021-08-19

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C7/22 ,  G11C7/10 ,  H03M1/82

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US12230361B2

公开(公告)日：2025-02-18

申请号：US18346565

申请日：2023-07-03

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  H03M1/82

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US11196435B1

公开(公告)日：2021-12-07

申请号：US17014536

申请日：2020-09-08

Applicant: Apple Inc.

Inventor： Pangjie Xu ,  Jelam K. Parekh ,  Mohamed H. Abu-Rahma

IPC: H03M1/06 ,  G04F10/00 ,  H03M7/16

Abstract: Systems, apparatuses, and methods for implementing an anti-aliasing technique for a time-to-digital converter are described. A pulse generator generates a pulse with a width that is representative of a voltage level of a supply voltage. A buffer chain receives the pulse from the pulse generator. A first sum is calculated by adding together a number of one bits in a first portion of the buffer chain. Also, a second sum is calculated by adding together a number of one bits in a second portion of the buffer chain. Then, a third sum is calculated by adding the first sum to the second sum if the first sum is saturated. Otherwise, the third sum is equal to the first sum if the first sum is not saturated. The third sum is used as a representation of the voltage level of the supply voltage.