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公开(公告)号：US20140344615A1
公开(公告)日：2014-11-20
申请号：US14218877
申请日：2014-03-18
Applicant: Apple Inc.
Inventor： William P. Cornelius , William O. Ferry , James E. Orr
CPC classification number: G06F1/266 , G06F1/06 , G06F3/14 , G09G5/006 , G09G2370/04 , G09G2370/045 , G09G2370/10 , G09G2370/12 , H01R29/00
Abstract: Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode.
Abstract translation: 允许符合多种标准的信号在电子设备上共享公共连接器的电路，方法和装置。 本发明的示例性实施例提供了一种连接器，其提供与一种模式中的传统标准兼容的信号和另一种模式中的较新标准的连接器。
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公开(公告)号：US20150092854A1
公开(公告)日：2015-04-02
申请号：US14039729
申请日：2013-09-27
Applicant: Apple Inc.
Inventor： James E. Orr , Timothy John Millet , Joseph J. Cheng , Nitin Bhargava , Guy Cote
IPC: H04N19/436 , H04N19/433 , H04N19/51 , H04N19/583 , H04N19/43
CPC classification number: H04N19/43 , G06T1/20 , H04N19/433 , H04N19/436 , H04N19/51 , H04N19/513
Abstract: A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.
Abstract translation: 一个块处理流水线，包括一个软件流水线和并行运行的硬件流水线。 软件管道在硬件管道之前至少运行一个程序段。 流水线的各个阶段可以各自包括在该阶段对当前块执行一个或多个操作的硬件流水线组件。 管道的至少一个阶段还可以包括软件流水线组件，该软件流水线组件在硬件组件正在处理当前块时，在流水线阶段确定用于处理下一个块的硬件组件的配置。 软件管线组件可以根据从流水线的上游级获得的与下一块相关的信息来确定配置。 软件管道组件还可以获得并使用与先前在该阶段处理的块相关的信息。
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公开(公告)号：US09215472B2
公开(公告)日：2015-12-15
申请号：US14039729
申请日：2013-09-27
Applicant: Apple Inc.
Inventor： James E. Orr , Timothy John Millet , Joseph J. Cheng , Nitin Bhargava , Guy Cote
IPC: G06T1/20 , G06T1/00 , G06F15/00 , H04N19/43 , H04N19/433 , H04N19/436 , H04N19/51 , H04N19/583 , H04N19/513
CPC classification number: H04N19/43 , G06T1/20 , H04N19/433 , H04N19/436 , H04N19/51 , H04N19/513
Abstract: A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.
Abstract translation: 一个块处理流水线，包括一个软件流水线和并行运行的硬件流水线。 软件管道在硬件管道之前至少运行一个程序段。 流水线的各个阶段可以各自包括在该阶段对当前块执行一个或多个操作的硬件流水线组件。 管道的至少一个阶段还可以包括软件流水线组件，该软件流水线组件在硬件组件正在处理当前块时，在流水线阶段确定用于处理下一个块的硬件组件的配置。 软件管线组件可以根据从流水线的上游级获得的与下一块相关的信息来确定配置。 软件管道组件还可以获得并使用与先前在该阶段处理的块相关的信息。
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公开(公告)号：US09274579B2
公开(公告)日：2016-03-01
申请号：US14218877
申请日：2014-03-18
Applicant: Apple Inc.
Inventor： William P. Cornelius , William O. Ferry , James E. Orr
CPC classification number: G06F1/266 , G06F1/06 , G06F3/14 , G09G5/006 , G09G2370/04 , G09G2370/045 , G09G2370/10 , G09G2370/12 , H01R29/00
Abstract: Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode.
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