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公开(公告)号：US08488379B2
公开(公告)日：2013-07-16
申请号：US13270995
申请日：2011-10-11
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
IPC: G11C14/00
CPC classification number: G11C14/0018
Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.
Abstract translation: 存储电路包括提供非易失性位的存储的高电压区域和提供至少部分存储易失性位的低电压区域。 高电压区域和低电压区域彼此隔离并且由在电流源和位线之间串联的多个晶体管形成。
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公开(公告)号：US20090168517A1
公开(公告)日：2009-07-02
申请号：US12006225
申请日：2007-12-31
Applicant: Andreas Scade , Stefan Guenther , Jeong-Mo Hwang
Inventor： Andreas Scade , Stefan Guenther , Jeong-Mo Hwang
CPC classification number: G11C16/0466
Abstract: A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.
Abstract translation: 一种操作具有串联布置在电压/电流源节点和调用汇聚节点之间的多个晶体管的非易失性存储器电路的方法包括在非易失性STANDBY期间在源节点和电荷存储晶体管之间的隔离晶体管上确定栅极偏置。
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公开(公告)号：US20090168519A1
公开(公告)日：2009-07-02
申请号：US12006226
申请日：2007-12-31
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
IPC: G11C14/00
CPC classification number: G11C14/00 , G11C11/405 , G11C11/4063 , G11C11/4097 , G11C14/0018
Abstract: A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.
Abstract translation: 操作存储器阵列的过程包括经由单个数据接口在nvDRAM单元阵列上执行所有易失性和非易失性操作，并且仅使用数据接口上的DRAM级信号。
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公开(公告)号：US20120113718A1
公开(公告)日：2012-05-10
申请号：US13270995
申请日：2011-10-11
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
IPC: G11C14/00
CPC classification number: G11C14/0018
Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.
Abstract translation: 存储电路包括提供非易失性位的存储的高电压区域和提供至少部分存储易失性位的低电压区域。 高电压区域和低电压区域彼此隔离并且由在电流源和位线之间串联的多个晶体管形成。
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公开(公告)号：US08064255B2
公开(公告)日：2011-11-22
申请号：US12006226
申请日：2007-12-31
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
CPC classification number: G11C14/00 , G11C11/405 , G11C11/4063 , G11C11/4097 , G11C14/0018
Abstract: A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.
Abstract translation: 操作存储器阵列的过程包括经由单个数据接口在nvDRAM单元阵列上执行所有易失性和非易失性操作，并且仅使用数据接口上的DRAM级信号。
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Patent Agency Ranking
公开(公告)号：US08059458B2
公开(公告)日：2011-11-15
申请号：US12006227
申请日：2007-12-31
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
IPC: G11C11/34
CPC classification number: G11C11/405 , G11C14/0018
Abstract: A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.
Abstract translation: 存储电路包括存储易失性和非易失性位电荷的单个晶体管。
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公开(公告)号：US07778098B2
公开(公告)日：2010-08-17
申请号：US12006224
申请日：2007-12-31
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
CPC classification number: G11C7/14
Abstract: A memory cell array includes reference cells each associated with a plurality of data cells of the array.
Abstract translation: 存储单元阵列包括每个与阵列的多个数据单元相关联的参考单元。
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公开(公告)号：US07675775B2
公开(公告)日：2010-03-09
申请号：US11999684
申请日：2007-12-05
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
IPC: G11C14/00
CPC classification number: G11C14/0018 , G11C14/0063
Abstract: A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.
Abstract translation: 存储器电路包括耦合到位线的易失性存储器单元，以及经由位线而非经由补码位线耦合到易失性存储器单元的非易失性存储单元。
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公开(公告)号：US20090168520A1
公开(公告)日：2009-07-02
申请号：US12006227
申请日：2007-12-31
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
CPC classification number: G11C11/405 , G11C14/0018
Abstract: A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.
Abstract translation: 存储电路包括存储易失性和非易失性位电荷的单个晶体管。
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公开(公告)号：US08036032B2
公开(公告)日：2011-10-11
申请号：US12006270
申请日：2007-12-31
Applicant: Andreas Scade , Stefan Guenther
Inventor： Andreas Scade , Stefan Guenther
IPC: G11C16/00
CPC classification number: G11C14/0018
Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.
Abstract translation: 存储电路包括提供非易失性位的存储的高电压区域和提供至少部分存储易失性位的低电压区域。 高电压区域和低电压区域彼此隔离并且由在电流源和位线之间串联的多个晶体管形成。
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