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1.
公开(公告)号:US11362649B1
公开(公告)日:2022-06-14
申请号:US17475205
申请日:2021-09-14
IPC分类号: H03K5/125 , H03K5/1252 , H03K3/037 , H03K19/21 , H03K5/00
摘要: A control signal may be produced in response to an assertion of a switch signal by asserting the control signal, waiting an adaptive delay after the assertion of the switch signal, de-asserting the control signal in response to the expiration of the adaptive delay, and re-asserting the control signal in response to a current generated according to the control signal becoming zero. The adaptive delay may be adjusted according to a voltage generated using the current. A circuit may include an XOR gate producing the control signal from a switch signal and an output of a Set-Reset Flip-Flop (SRFF), a zero-detect circuit that resets the SRFF when a current generated using the control circuit becomes zero, and a delay circuit to set the SRFF an adaptive delay after assertion of the switch signal and to adjust the adaptive delay according to a voltage generated by the current.
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公开(公告)号:US11689170B2
公开(公告)日:2023-06-27
申请号:US17014948
申请日:2020-09-08
发明人: Sam Seiichiro Ochi
IPC分类号: H03H1/00 , H03H7/42 , H01R13/719
CPC分类号: H03H1/0007 , H01R13/719 , H03H7/427
摘要: A transient noise reduction filter comprises a cable including one or more twisted pairs of conductors and one or more common mode chokes (CMCs). The one or more CMCs a formed from respective pluralities of turns of the cable. Each of the CMCs may be a magnetic CMC wherein the plurality of turns of the cable are wrapped around a magnetic core, or an air-core CMC wherein the plurality of turns of the cable are not wrapped around a magnetic core but are instead disposed around a non-magnetic material (such as air)
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公开(公告)号:US12081177B2
公开(公告)日:2024-09-03
申请号:US17475234
申请日:2021-09-14
发明人: Sam Seiichiro Ochi , Dumitru Gheorge Sdrulla , W. Albert Gu , Tetsuya Takata , Itsuo Yuzurihara , Tomohiro Yoneyama , Yu Hosoyamada
IPC分类号: H03F3/217
CPC分类号: H03F3/217 , H03F2200/451
摘要: A full-bridge class-D amplifier circuit comprises first through fourth power devices. First conduction terminals of the first and third power devices are coupled to a first power supply voltage, and second conduction terminals of the second and fourth power devices are coupled to a second power supply voltage. A second conduction terminal of the first power device and a first conduction terminal of the second power device are coupled to a first amplifier output. A second conduction terminal of the third power device and a first conduction terminal of the fourth power device are coupled to a second amplifier output. Left and right driver devices respectively disposed adjacent to left and right sides of the first power device have outputs respectively coupled to left and right control terminals respectively disposed on the left and right sides of the first power device.
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