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公开(公告)号：US20170117602A1
公开(公告)日：2017-04-27
申请号：US14922037
申请日：2015-10-23
Applicant: Analog Devices Global
Inventor： Conor John McLoughlin , Michael John Flynn , Laurence B. O'Sullivan , Shane Geary , Stephen O'Brien , Bernard P. Stenson , Baoxing Chen , Sarah Carroll , Michael Morrissey , Patrick M. McGuinness
CPC classification number: H01P1/36 , H01L2224/48137 , H01P5/187
Abstract: An isolator device and a corresponding method of forming the isolator device to include first and second electrodes, a layer of first dielectric material between the first and second electrodes, and at least one region of second dielectric material between the layer of first dielectric material and at least one of the first and second electrodes. The second dielectric material has a higher relative permittivity than the first dielectric material.
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公开(公告)号：US11044022B2
公开(公告)日：2021-06-22
申请号：US16287796
申请日：2019-02-27
Applicant: Analog Devices Global Unlimited Company
Inventor： Laurence B. O'Sullivan , Shane Geary , Baoxing Chen , Bernard Patrick Stenson , Paul Lambkin , Patrick M. McGuinness , Stephen O'Brien , Patrick J. Murphy
Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Discrete dielectric regions positioned between isolator components forming an isolator provide electrical isolation between the isolator components as well as between the isolators formed on the substrate. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.
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公开(公告)号：US09941565B2
公开(公告)日：2018-04-10
申请号：US14922037
申请日：2015-10-23
Applicant: Analog Devices Global
Inventor： Conor John McLoughlin , Michael John Flynn , Laurence B. O'Sullivan , Shane Geary , Stephen O'Brien , Bernard P. Stenson , Baoxing Chen , Sarah Carroll , Michael Morrissey , Patrick M. McGuinness
CPC classification number: H01P1/36 , H01L2224/48137 , H01P5/187
Abstract: An isolator device and a corresponding method of forming the isolator device to include first and second electrodes, a layer of first dielectric material between the first and second electrodes, and at least one region of second dielectric material between the layer of first dielectric material and at least one of the first and second electrodes. The second dielectric material has a higher relative permittivity than the first dielectric material.
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Patent Agency Ranking
公开(公告)号：US10672968B2
公开(公告)日：2020-06-02
申请号：US14805135
申请日：2015-07-21
Applicant: Analog Devices Global
Inventor： Patrick M. McGuinness , Helen Berney , Jane Cornett , William Alan Lane , Baoxing Chen
Abstract: An embodiment of a thermoelectric device may include a plurality of thermoelectric cells disposed between first and second planes. Each of the thermoelectric cells may include a thermoelectric element formed from a thermoelectric material of a single semiconductor type, the thermoelectric element including a first end, a second end, and a portion extending from the first end to the second end, the portion extending from the first end to the second end including at least two surfaces that face each other; and at least one conductive element electrically connected to and extending away from the second end of the thermoelectric element toward the first end of the thermoelectric element of another thermoelectric cell. Each thermoelectric cell also may further include an insulating element disposed between the at least two surfaces of the thermoelectric element and between portions of the at least one conductive element.
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公开(公告)号：US20200076512A1
公开(公告)日：2020-03-05
申请号：US16287796
申请日：2019-02-27
Applicant: Analog Devices Global Unlimited Company
Inventor： Laurence B. O'Sullivan , Shane Geary , Baoxing Chen , Bernard Patrick Stenson , Paul Lambkin , Patrick M. McGuinness , Stephen O'Brien , Patrick J. Murphy
Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Discrete dielectric regions positioned between isolator components forming an isolator provide electrical isolation between the isolator components as well as between the isolators formed on the substrate. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.
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公开(公告)号：US10677822B2
公开(公告)日：2020-06-09
申请号：US15708958
申请日：2017-09-19
Applicant: Analog Devices Global Unlimited Company
Inventor： David J. Clarke , Stephen Denis Heffernan , Alan J. O'Donnell , Patrick M. McGuinness
IPC: G01R31/00 , G01R19/165 , H01L23/60 , H01L27/02 , G01R31/28 , G01N25/04 , H01L23/525 , H01L23/62 , H01L25/065
Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.
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公开(公告)号：US20180130867A1
公开(公告)日：2018-05-10
申请号：US15347724
申请日：2016-11-09
Applicant: Analog Devices Global
Inventor： Paul Lambkin , Michal J. Osiak , Brian Anthony Moane , Stephen O'Brien , Laurence Brendan O'Sullivan , Patrick J. Murphy , Patrick M. McGuinness , Bernard P. Stenson
CPC classification number: H01L28/10 , H01F27/2804 , H01F27/2885 , H01F27/323 , H01F41/041 , H01F41/042 , H01F41/122 , H01F2019/085 , H01F2027/2809 , H01F2027/2819 , H01L23/5227
Abstract: A magnetic isolator is described. The magnetic isolator may comprise a top conductive coil, a bottom conductive coil, and a dielectric layer separating the top conductive coil from the bottom conductive coil. The top conductive coil may comprise an outermost portion having multiple segments. The segments may be configured to reduce the peak electric field in a region of the dielectric layer near the outer edge of the top conductive coil. The top conductive coil may comprise a first lateral segment, and a second lateral segment that is laterally offset with respect to the first lateral segment. The first lateral segment may be closer to the center of the top conductive coil than the second lateral segment, and may be closer to the bottom conductive coil than the second lateral segment. The magnetic isolator may be formed using microfabrication techniques.
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公开(公告)号：US20180088155A1
公开(公告)日：2018-03-29
申请号：US15708958
申请日：2017-09-19
Applicant: Analog Devices Global Unlimited Company
Inventor： David J. Clarke , Stephen Denis Heffernan , Alan J. O'Donnell , Patrick M. McGuinness
IPC: G01R19/165 , H01L23/62 , H01L23/525 , G01N25/04 , G01R31/28
Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.
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