公开(公告)号：US20060025945A1

公开(公告)日：2006-02-02

申请号：US11235856

申请日：2005-09-27

Applicant: Alain Blanc ,  Patrick Jeanniot

Inventor： Alain Blanc ,  Patrick Jeanniot

IPC: G06F19/00

CPC classification number: H04L25/03343 ,  H04L1/0001 ,  H04L1/20 ,  H04L7/0337 ,  H04L2025/03375

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract translation: 公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。 根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。 在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。 在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。 最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。

公开(公告)号：US06990418B2

公开(公告)日：2006-01-24

申请号：US10697832

申请日：2003-10-30

Applicant: Alain Blanc ,  Patrick Jeanniot

Inventor： Alain Blanc ,  Patrick Jeanniot

IPC: G01R13/00 ,  H04B17/00

CPC classification number: H04L25/03343 ,  H04L1/0001 ,  H04L1/20 ,  H04L7/0337 ,  H04L2025/03375

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

公开(公告)号：US07668672B2

公开(公告)日：2010-02-23

申请号：US11764453

申请日：2007-06-18

Applicant: Alain Blanc ,  Patrick Jeanniot

Inventor： Alain Blanc ,  Patrick Jeanniot

IPC: G01R13/00 ,  H04B17/00

CPC classification number: H04L25/03343 ,  H04L1/0001 ,  H04L1/20 ,  H04L7/0337 ,  H04L2025/03375

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract translation: 公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。 根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。 在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。 在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。 最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。

公开(公告)号：US07477685B2

公开(公告)日：2009-01-13

申请号：US11774572

申请日：2007-07-07

Applicant: Alain Blanc ,  Patrick Jeanniot

Inventor： Alain Blanc ,  Patrick Jeanniot

IPC: H04B3/46 ,  H04Q1/20

CPC classification number: H04L1/20

Abstract: Methods and systems for analyzing the quality of high-speed signals are provided, wherein a high speed signal is sampled simultaneously a plurality of times during a sampling clock period at each of a plurality of phase rotator positions to generate a plurality of partial values, wherein subset pluralities of the partial values are associated to phase rotator positions. The partial values are combined into a global value which is analyzed to determine a quality of the high speed signal. Phase rotator behavior may also be analyzed to determine signal quality. A best position to lock a phase rotator when determining signal quality may be determined from a graphic characterization of a phase rotator position distribution.

Abstract translation: 提供了用于分析高速信号质量的方法和系统，其中在多个相位旋转器位置中的每个相位旋转器位置处的采样时钟周期期间，高速信号被同时多次采样以产生多个部分值，其中 子集多个部分值与相位旋转器位置相关联。 将部分值组合成全局值，该值被分析以确定高速信号的质量。 也可以分析相位旋转器行为以确定信号质量。 确定信号质量时锁定相位旋转器的最佳位置可以从相位旋转器位置分布的图形表征来确定。

公开(公告)号：US20070271050A1

公开(公告)日：2007-11-22

申请号：US11764453

申请日：2007-06-18

Applicant: Alain Blanc ,  Patrick Jeanniot

Inventor： Alain Blanc ,  Patrick Jeanniot

IPC: G06F19/00

CPC classification number: H04L25/03343 ,  H04L1/0001 ,  H04L1/20 ,  H04L7/0337 ,  H04L2025/03375

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract translation: 公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。 根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。 在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。 在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。 最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。

公开(公告)号：US5220327A

公开(公告)日：1993-06-15

申请号：US878106

申请日：1992-05-04

Applicant: Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Orengo ,  Gerard Richter

Inventor： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Orengo ,  Gerard Richter

IPC: H04B14/06 ,  H03H17/06

CPC classification number: H03H17/0614 ,  H03H17/0664

Abstract: A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##

公开(公告)号：US4941151A

公开(公告)日：1990-07-10

申请号：US252303

申请日：1988-10-03

Applicant: Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Eric Lallemand

Inventor： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Eric Lallemand

IPC: H04L7/033

CPC classification number: H04L7/0331

Abstract: A predictive clock extracting circuit having a first circuit for determining the duration between two consecutive transitions of a multilevel digital signal and a second circuit for generating an SPL pulse at half the duration after a third transition following on two consecutive previous transitions. A phase locked oscillator which is driven by said SPL pulse generates the extracted clock signal which is in phase with the SPL pulse and coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs. The result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. The preferred embodiment of the invention also involves an up/down counter K which generates a second counter K(i) that is expected to be representative of half the value of the first counter N(i). Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor.

公开(公告)号：US20080013615A1

公开(公告)日：2008-01-17

申请号：US11774572

申请日：2007-07-07

Applicant: Alain Blanc ,  Patrick Jeanniot

Inventor： Alain Blanc ,  Patrick Jeanniot

IPC: H04B3/46

CPC classification number: H04L1/20

Abstract: Methods and systems for analyzing the quality of high-speed signals are provided, wherein a high speed signal is sampled simultaneously a plurality of times during a sampling clock period at each of a plurality of phase rotator positions to generate a plurality of partial values, wherein subset pluralities of the partial values are associated to phase rotator positions. The partial values are combined into a global value which is analyzed to determine a quality of the high speed signal. Phase rotator behavior may also be analyzed to determine signal quality. A best position to lock a phase rotator when determining signal quality may be determined from a graphic characterization of a phase rotator position distribution.

Abstract translation: 提供了用于分析高速信号质量的方法和系统，其中在多个相位旋转器位置中的每个相位旋转器位置处的采样时钟周期期间，高速信号被同时多次采样以产生多个部分值，其中 子集多个部分值与相位旋转器位置相关联。 将部分值组合成全局值，该值被分析以确定高速信号的质量。 也可以分析相位旋转器行为以确定信号质量。 确定信号质量时锁定相位旋转器的最佳位置可以从相位旋转器位置分布的图形表征来确定。

公开(公告)号：US5461641A

公开(公告)日：1995-10-24

申请号：US981157

申请日：1992-11-23

Applicant: Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Richter

Inventor： Jean-Claude Abbiate ,  Alain Blanc ,  Patrick Jeanniot ,  Gerard Richter

IPC: H03M3/04 ,  H03H17/06 ,  H04B14/04

CPC classification number: H03H17/0664

Abstract: A Decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of Pulse Coded Modulation (PCM) samples in accordance with the formula ##EQU1## where Cn is the sequence of the coefficients of the decimation filter which corresponds to a determined decimation factor, and the PCM samples being processed by a Digital Signal Processor (DSP). The decimation filter includes a device for storing a digital value representative of the DC component introduced during the sigma-delta coding process, with the digital value being computing by the DSP processor during an initialization phase. The decimation filter further includes a device operating after the latter initialization phase for subtracting the stored digital value from each of the PCM samples so that the resulting sequence of PCM samples appears free of any DC component introduced during the sigma-delta coding. This accurate DC component suppression is achieved without necessitating the use of additional digital signal processor resources from the processor. Preferably, the decimation filter comprises a device for detecting a saturation occurring in the computing of the PCM sample, and responsive to the saturation detection, for transmitting a predetermined PCM sample to the DSP processor.

Abstract translation: 一种抽取滤波器，用于根据与之对应的抽取滤波器的公式来将与Σ-Δ时钟（fs）同步的Σ-Δ脉冲序列转换成脉冲编码调制（PCM）采样序列 到确定的抽取因子，并且PCM采样由数字信号处理器（DSP）处理。 抽取滤波器包括用于存储代表在Σ-Δ编码处理期间引入的DC分量的数字值的装置，数字值由DSP处理器在初始化阶段期间计算。 抽取滤波器还包括在后一初始化阶段之后操作的装置，用于从每个PCM样本中减去所存储的数字值，使得所得到的PCM样本序列在Σ-Δ编码期间不会出现任何DC分量。 实现这种精确的DC分量抑制，而不需要使用来自处理器的附加数字信号处理器资源。 优选地，抽取滤波器包括用于检测在PCM采样的计算中出现的饱和度并且响应饱和检测用于将预定的PCM采样发送到DSP处理器的装置。

公开(公告)号：US4845752A

公开(公告)日：1989-07-04

申请号：US917945

申请日：1986-10-14

Applicant: Alain Blanc ,  Patrick Jeanniot ,  Sylvie Spalmacin-Roma

Inventor： Alain Blanc ,  Patrick Jeanniot ,  Sylvie Spalmacin-Roma

IPC: H04Q11/04 ,  G06F9/48 ,  G06F13/22 ,  H04B1/66 ,  H04J3/06 ,  H04M1/253

CPC classification number: G06F9/4825 ,  G06F13/22 ,  H04B1/667 ,  H04J3/0626 ,  H04M1/253

Abstract: A multiprocessor system includes a plurality of signal processors and a common unit processor. Each of the signal processors is connected to a different source of signals such as voice signals and performs one or more signal processing functions relative to the connected source. The common unit processor performs one or more functions for the signal processors on a shared synchronized basis. A signal processor adapter responsive to a source of clock pulses generates synchronous interrupts applied to the common unit processor and enabling signals in sequence to connect the signal processor in sequence to the common unit processor in synchronization with the interrupts. In addition, the signal processors are provided with ping-pong buffers at their inputs and outputs to enhance throughput.

Abstract translation: 多处理器系统包括多个信号处理器和公共单元处理器。 每个信号处理器连接到诸如语音信号的不同信号源，并且相对于所连接的源执行一个或多个信号处理功能。 公共单元处理器在共享同步的基础上对信号处理器执行一个或多个功能。 响应于时钟脉冲源的信号处理器适配器产生施加到公共单元处理器的同步中断，并且依次使能信号将信号处理器顺序地连接到与中断同步的公共单元处理器。 此外，信号处理器在其输入和输出端提供乒乓缓冲器以提高吞吐量。