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1.发明授权公开(公告)号：US11567554B2
公开(公告)日：2023-01-31
申请号：US15837918
申请日：2017-12-11
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Jay Fleischman , Michael Estlick , Michael Christopher Sedmak , Erik Swanson , Sneha V. Desai
Abstract: A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.
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公开(公告)号：US12118411B2
公开(公告)日：2024-10-15
申请号：US16568038
申请日：2019-09-11
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Sneha V. Desai , Michael Estlick , Erik Swanson , Anilkumar Ranganagoudra
CPC classification number: G06F9/544 , G06F9/505 , G06F9/5083 , G06F9/528 , G06F9/546
Abstract: A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.
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Patent Agency Ranking
3.发明授权公开(公告)号：US10776123B2
公开(公告)日：2020-09-15
申请号：US16207548
申请日：2018-12-03
Applicant: Advanced Micro Devices, Inc.
Inventor： Erik D. Swanson , Michael Estlick , Sneha V. Desai
IPC: G06F9/38
Abstract: Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.
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公开(公告)号：US20200174796A1
公开(公告)日：2020-06-04
申请号：US16207548
申请日：2018-12-03
Applicant: Advanced Micro Devices, Inc.
Inventor： Erik D. Swanson , Michael Estlick , Sneha V. Desai
Abstract: Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.
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公开(公告)号：US11709681B2
公开(公告)日：2023-07-25
申请号：US15837974
申请日：2017-12-11
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Jay Fleischman , Michael Estlick , Michael Christopher Sedmak , Erik Swanson , Sneha V. Desai
IPC: G06F9/38
CPC classification number: G06F9/3867 , G06F9/3836
Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.
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公开(公告)号：US11451241B2
公开(公告)日：2022-09-20
申请号：US15842027
申请日：2017-12-14
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Erik Swanson , Sneha V. Desai , Michael Estlick
IPC: G06F12/08 , H03M7/20 , G06F16/16 , G06F16/903 , G06F12/0891
Abstract: A processor employs a set of bits to indicate values of portions of registers of a register file. In response to a specified instruction indicating an expected change of instruction types to be executed, the processor sets one or more of the bits and, for subsequent instructions, interprets corresponding portions of the registers as having a specified value (e.g., zero). By employing the set of bits to set the values of the register portions, rather than setting the individual portions of the registers to the specified value, the processor conserves processor resources (e.g., power) when the processor transitions between executing instructions of different types.
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公开(公告)号：US11281466B2
公开(公告)日：2022-03-22
申请号：US16660495
申请日：2019-10-22
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Arun A. Nair , Michael Estlick , Erik Swanson , Sneha V. Desai , Donglin Ji
Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.
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