公开(公告)号：US12009025B2

公开(公告)日：2024-06-11

申请号：US17358527

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Tawfik Ahmed ,  Andrew J. Robison ,  Russell J. Schreiber

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.

公开(公告)号：US20220208234A1

公开(公告)日：2022-06-30

申请号：US17133956

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US11610879B2

公开(公告)日：2023-03-21

申请号：US16226311

申请日：2018-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Richard M. Born ,  Carl D. Dietz ,  William A. Halliday

IPC: H01L27/02 ,  H03K19/00 ,  H01L23/495 ,  H01L25/04 ,  G06F1/26 ,  H01L23/498

Abstract: A handshake mechanism allows die discovery in a stacked die architecture that keeps inputs isolated until the handshake is complete. Power good indications are used as handshake signals between the die. A die keeps inputs isolated from above until a power good indication from the die above indicates presence of the die above. The die keeps inputs isolated from below until the die detects power is good and receives a power good indication from the die and the die below. In an implementation drivers and receivers, apart from configuration bus drivers and receivers are disabled until a fuse distribution done signal indicates that repairs have been completed. Drivers are then enabled and after a delay to ensure signals are driven, receivers are deisolated. A top die in the die stack never sees a power good indication from a die above and therefore keeps inputs from above isolated. That allows the height of the die stack to be unknown at power on.

公开(公告)号：US11514956B2

公开(公告)日：2022-11-29

申请号：US17133956

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US20220366945A1

公开(公告)日：2022-11-17

申请号：US17359253

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Russell J. Schreiber

IPC: G11C7/10 ,  G11C7/12 ,  H03K19/173

Abstract: A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.

公开(公告)号：US12165700B2

公开(公告)日：2024-12-10

申请号：US17488519

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu ,  Keith A. Kasprak

IPC: G11C11/419 ,  G11C11/418

Abstract: A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.

公开(公告)号：US11854652B2

公开(公告)日：2023-12-26

申请号：US17984796

申请日：2022-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

CPC classification number: G11C7/065

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US11527270B2

公开(公告)日：2022-12-13

申请号：US17359253

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Russell J. Schreiber

IPC: G11C7/00 ,  G11C7/10 ,  H03K19/173 ,  G11C7/12

Abstract: A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.

公开(公告)号：US20220358996A1

公开(公告)日：2022-11-10

申请号：US17359254

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C7/10

Abstract: A write masked latch bit cell of an SRAM includes a write mask circuit that is responsive to assertion of a first write mask signal to cause a value of a write data node to be a first value and is responsive to assertion of a second write mask signal to cause the value of the write data node to have a second value. A pass gate supplies the data on the write data node to an internal node of the bit cell responsive to write word line signals being asserted. A keeper circuit maintains the value of the first node independently of values of the write word line signals while the first write mask signal and the second write mask signal are deasserted.

公开(公告)号：US20210141733A1

公开(公告)日：2021-05-13

申请号：US16680491

申请日：2019-11-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber

IPC: G06F12/0877 ,  G06F12/06 ,  G06F12/02 ,  G11C8/12 ,  G11C7/10

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.