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公开(公告)号：US20150006810A1
公开(公告)日：2015-01-01
申请号：US13929040
申请日：2013-06-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric W. Busta , Karthik Natarajan , Brian M. Lay , Gregory A. Constant
IPC: G11C7/10
CPC classification number: G11C8/16 , G06F9/3012 , G11C7/1075 , G11C2207/007
Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.
Abstract translation: 寄存器文件包括基板，多个入口和多个读取端口。 每个条目包括限定在基板上的多个存储器单元的相应子集。 每个读取端口包括限定在基板上的多个访问元件。 每个访问元素与每个条目的特定公共位位置相关联。 多个入口访问组被布置在基板上的相邻列中。 每个条目访问组与多个条目中的相应一个条目相关联，并且包括用于相应条目的所有读取端口的访问元素。
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公开(公告)号：US20140325187A1
公开(公告)日：2014-10-30
申请号：US13869488
申请日：2013-04-24
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Michael D. Estlick , Jay E. Fleischman , Kevin A. Hurd , Mark M. Gibson , Kelvin D. Goveas , Brian M. Lay
IPC: G06F9/30
CPC classification number: G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/3873 , G06F9/3889
Abstract: A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.
Abstract translation: 一种方法包括：将第一单周期指令分配给选择用于以程序顺序执行的单周期指令的第一流水线。 该方法还包括将第一单周期指令的至少一个源寄存器标记为准备在第一流水线中执行，以响应分配给第一管线的所有较早的单循环指令准备好并且有资格被选择执行。 一种装置包括解码器，用于对第一单周期指令进行解码，并将第一单周期指令分配给第一流水线。 该装置还包括一个调度器，用于以程序顺序挑选由第一流水线执行的单周期指令，并且响应于确定所有第一单循环指令的所有第一单循环指令的至少一个源寄存器准备好在第一流水线中执行 分配给第一个管道的较旧的单循环指令已准备就绪并符合条件。
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公开(公告)号：US09959122B2
公开(公告)日：2018-05-01
申请号：US13869488
申请日：2013-04-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael D. Estlick , Jay E. Fleischman , Kevin A. Hurd , Mark M. Gibson , Kelvin D. Goveas , Brian M. Lay
CPC classification number: G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/3873 , G06F9/3889
Abstract: A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.
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公开(公告)号：US09779792B2
公开(公告)日：2017-10-03
申请号：US13929040
申请日：2013-06-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric W. Busta , Karthik Natarajan , Brian M. Lay , Gregory A. Constant
CPC classification number: G11C8/16 , G06F9/3012 , G11C7/1075 , G11C2207/007
Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.
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