公开(公告)号：US20140325187A1

公开(公告)日：2014-10-30

申请号：US13869488

申请日：2013-04-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael D. Estlick ,  Jay E. Fleischman ,  Kevin A. Hurd ,  Mark M. Gibson ,  Kelvin D. Goveas ,  Brian M. Lay

IPC: G06F9/30

CPC classification number: G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3873 ,  G06F9/3889

Abstract: A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.

Abstract translation: 一种方法包括：将第一单周期指令分配给选择用于以程序顺序执行的单周期指令的第一流水线。 该方法还包括将第一单周期指令的至少一个源寄存器标记为准备在第一流水线中执行，以响应分配给第一管线的所有较早的单循环指令准备好并且有资格被选择执行。 一种装置包括解码器，用于对第一单周期指令进行解码，并将第一单周期指令分配给第一流水线。 该装置还包括一个调度器，用于以程序顺序挑选由第一流水线执行的单周期指令，并且响应于确定所有第一单循环指令的所有第一单循环指令的至少一个源寄存器准备好在第一流水线中执行 分配给第一个管道的较旧的单循环指令已准备就绪并符合条件。

公开(公告)号：US09317250B2

公开(公告)日：2016-04-19

申请号：US13674220

申请日：2012-11-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Kelvin D. Goveas ,  Debjit Das Sarma ,  Scott A. Hilker ,  Hanbing Liu

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/544

CPC classification number: G06F7/483 ,  G06F7/49936 ,  G06F7/5443

Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.

Abstract translation: 本申请提供了一种用于支持浮点乘法单元（FMAC）中的反常数的方法和装置。 FMAC的一个实施例可配置为将第一和第二操作数的乘积添加到第三操作数。 FMAC的该实施例可配置为通过从乘积的乘积指数减去最小正态指数来确定乘积和第三操作数之和的最小指数偏移。 如果FMAC的这个实施例如果第三操作数的第三指数小于或等于乘积指数并且最小指数移位小于或等于，则可配置为使表示和的位移动移位最小指数移位 到总和的预测左移。

公开(公告)号：US09959122B2

公开(公告)日：2018-05-01

申请号：US13869488

申请日：2013-04-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael D. Estlick ,  Jay E. Fleischman ,  Kevin A. Hurd ,  Mark M. Gibson ,  Kelvin D. Goveas ,  Brian M. Lay

IPC: G06F15/00 ,  G06F9/46 ,  G06F9/38

CPC classification number: G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3873 ,  G06F9/3889

Abstract: A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.