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公开(公告)号：US09905144B2
公开(公告)日：2018-02-27
申请号：US14710605
申请日：2015-05-13
Applicant: AU Optronics Corp.
Inventor： Nan-Ying Lin , Chung-Lin Fu , Yu-Hsin Ting
CPC classification number: G09G3/006 , G09G3/36 , G09G2330/12
Abstract: A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and N switches. N is a positive integer. The signal pads are configured to receive a test data signal, a voltage signal, an enable signal and a plurality of first switch control signals. The first data distributor distributes the test data signal to N output terminals of the first data distributor. Each of the logic circuit units generates a second switch control signal according to the voltage signal, the enable signal and a corresponding one of the first switch control signals. Each of the switches controls the electrical connection between an output terminal of the first data distributor coupled thereto and at least a data line coupled thereto.
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公开(公告)号：US09330622B2
公开(公告)日：2016-05-03
申请号：US13897451
申请日：2013-05-20
Applicant: AU Optronics Corp.
Inventor： Yi-Xuan Hung , Yu-Hsin Ting , Chen-Ming Chen , I-Fang Chen , Da-Wei Fan
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3607 , G09G2300/0426 , G09G2300/0452 , G09G2300/0465 , G09G2320/0209 , G09G2320/0233
Abstract: A display includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The scan lines and the data lines are coupled to the pixels. Two color sub-pixels in the same row coupled to the same data line are coupled to different scan lines, and all of the second color sub-pixels in the same row are coupled to the same scan line.
Abstract translation: 显示器包括多个像素，多条扫描线和多条数据线。 每个像素包括第一颜色子像素，第二彩色子像素和第三颜色子像素。 扫描线和数据线耦合到像素。 耦合到相同数据线的同一行中的两个彩色子像素耦合到不同的扫描线，并且同一行中的所有第二彩色子像素耦合到相同的扫描线。
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公开(公告)号：US09847138B2
公开(公告)日：2017-12-19
申请号：US15061160
申请日：2016-03-04
Applicant: AU OPTRONICS CORP.
Inventor： Pei-Hua Chen , Yu-Hsin Ting , Chung-Lin Fu , Tsao-Wen Lu , Nan-Ying Lin , Wei-Chun Hsu
CPC classification number: G11C19/28 , G09G3/3648 , G09G3/3677 , G09G3/38 , G09G2310/0286 , G11C19/00 , G11C19/184
Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.
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公开(公告)号：US08983020B2
公开(公告)日：2015-03-17
申请号：US13897506
申请日：2013-05-20
Applicant: AU Optronics Corp.
Inventor： Ling-Ying Chien , Kuang-Hsiang Liu , Yu-Hsin Ting
CPC classification number: G09G3/3674 , G09G3/3677 , G09G2310/0286 , G09G2320/0209 , G09G2320/0233 , G11C19/28
Abstract: A shift register circuit includes a first shift register string and a second shift register string. The first shift register string is configured to receive a first start signal and output a first-stage control signal. The second shift register string, electrically connected to the first shift register string, is configured to receive the first-stage control signal and a second start signal and output the first pulse of a first-stage scan signal according to the first-stage control signal and the second start signal and consequently output the second pulse of the first-stage scan signal according to the second start signal; wherein the first and second pulses are configured to have different pulse widths. A driving method of a shift register circuit is also provided.
Abstract translation: 移位寄存器电路包括第一移位寄存器串和第二移位寄存器串。 第一移位寄存器串被配置为接收第一起始信号并输出第一级控制信号。 电连接到第一移位寄存器串的第二移位寄存器串被配置为接收第一级控制信号和第二起始信号，并且根据第一级控制信号输出第一级扫描信号的第一脉冲 和第二起始信号，从而根据第二起始信号输出第一级扫描信号的第二脉冲; 其中所述第一和第二脉冲被配置为具有不同的脉冲宽度。 还提供了一种移位寄存器电路的驱动方法。
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公开(公告)号：US20140132651A1
公开(公告)日：2014-05-15
申请号：US13897451
申请日：2013-05-20
Applicant: AU Optronics Corp.
Inventor： Yi-Xuan Hung , Yu-Hsin Ting , Chen-Ming Chen , I-Fang Chen , Da-Wei Fan
IPC: G09G5/10
CPC classification number: G09G3/3648 , G09G3/3607 , G09G2300/0426 , G09G2300/0452 , G09G2300/0465 , G09G2320/0209 , G09G2320/0233
Abstract: A display includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The scan lines and the data lines are coupled to the pixels. Two color sub-pixels in the same row coupled to the same data line are coupled to different scan lines, and all of the second color sub-pixels in the same row are coupled to the same scan line.
Abstract translation: 显示器包括多个像素，多条扫描线和多条数据线。 每个像素包括第一颜色子像素，第二彩色子像素和第三颜色子像素。 扫描线和数据线耦合到像素。 耦合到相同数据线的同一行中的两个彩色子像素耦合到不同的扫描线，并且同一行中的所有第二彩色子像素耦合到相同的扫描线。
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Patent Agency Ranking
公开(公告)号：US09318064B2
公开(公告)日：2016-04-19
申请号：US13661239
申请日：2012-10-26
Applicant: AU OPTRONICS CORP.
Inventor： Pei-Hua Chen , Yu-Hsin Ting , Chung-Lin Fu , Tsao-Wen Lu , Nan-Ying Lin , Wei-Chun Hsu
CPC classification number: G11C19/28 , G09G3/3648 , G09G3/3677 , G09G3/38 , G09G2310/0286 , G11C19/00 , G11C19/184
Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.
Abstract translation: 移位寄存器包括移位寄存器单元，其中至少一个移位寄存器单元耦合到林格移位寄存器单元和后级移位寄存器单元，其中至少一个移位寄存器单元包括信号输入电路，信号输出 电路，下拉电路和开关电路。 电连接到林间移位寄存器单元的信号输入电路可以从林格移位寄存器接收逻辑信号。 信号输出电路经由控制信号端子电耦合到信号输入电路，并且电耦合到后级移位寄存器单元。 输出到电路的信号可以接收第一个时钟信号。 下拉电路通过开关电路与控制信号端子电耦合或电隔离。
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公开(公告)号：US09236019B2
公开(公告)日：2016-01-12
申请号：US14300776
申请日：2014-06-10
Applicant: AU OPTRONICS CORP.
Inventor： Yu-Hsin Ting , Wei-Chun Hsu , Chung-Lin Fu , Chung-Hung Chen , Chin-Tang Chuang
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G2310/0251 , G09G2310/0297
Abstract: A display device includes multiple pixels, a gate driver and a data driver. Each pixel includes a transistor and a pixel capacitor electrically coupled to the transistor. The gate driver is configured to turn on the transistor of a first pixel for one time during a first turn-on period of multiple turn-on cycles of a frame cycle of a frame displayed by the display device. The data driver is configured to charge the pixel capacitor of the first pixel via the transistor of the first pixel to a first over-charge voltage and a data voltage during an over-charge period and a recovery period of the first turn-on period. The first over-charge voltage is different from the data voltage. A method for driving the display device is also provided.
Abstract translation: 显示装置包括多个像素，栅极驱动器和数据驱动器。 每个像素包括电耦合到晶体管的晶体管和像素电容器。 栅极驱动器被配置为在由显示装置显示的帧的帧周期的多个接通周期的第一接通周期期间将第一像素的晶体管导通一次。 数据驱动器被配置为经由第一像素的晶体管将第一像素的像素电容器充电到第一过充电电压，并且在过充电期间的数据电压和第一导通周期的恢复周期。 第一个过充电电压与数据电压不同。 还提供了一种用于驱动显示装置的方法。
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公开(公告)号：US09400566B2
公开(公告)日：2016-07-26
申请号：US14062381
申请日：2013-10-24
Applicant: AU OPTRONICS CORP.
Inventor： Wei-Chun Hsu , Yu-Hsin Ting , Wei-Chih Lee , Chung-Lin Fu , Nan-Ying Lin
CPC classification number: G06F3/03 , G09G3/3614 , G09G3/3655 , G09G2310/06
Abstract: A driving method for a display panel is provided. The display panel includes at least a first common signal line, at least a second common signal line and a plurality of pixels arranged as a pixel array. The pixel array includes a first pixel row and a second pixel row electrically connected to the first common signal line and the second common signal line, respectively. The driving method includes steps of: generating a first AC common signal; generating a second AC common signal, wherein the first AC common signal and the second AC common signal are inverse to each other; and providing the first and second AC common signal to the first and second pixel rows through the first and second common signal lines, respectively, by way of N-frame switch, wherein N is a positive integer.
Abstract translation: 提供了一种用于显示面板的驱动方法。 显示面板至少包括第一公共信号线，至少第二公共信号线和排列成像素阵列的多个像素。 像素阵列包括分别电连接到第一公共信号线和第二公共信号线的第一像素行和第二像素行。 驱动方法包括以下步骤：产生第一AC公共信号; 产生第二AC公共信号，其中所述第一AC公共信号和所述第二AC公共信号彼此相反; 以及通过N帧开关分别通过第一和第二公共信号线将第一和第二AC公共信号提供给第一和第二像素行，其中N是正整数。
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公开(公告)号：US20160189798A1
公开(公告)日：2016-06-30
申请号：US15061160
申请日：2016-03-04
Applicant: AU OPTRONICS CORP.
Inventor： Pei-Hua CHEN , Yu-Hsin Ting , Chung-Lin Fu , Tsao-Wen Lu , Nan-Ying Lin , Wei-Chun Hsu
IPC: G11C19/28
CPC classification number: G11C19/28 , G09G3/3648 , G09G3/3677 , G09G3/38 , G09G2310/0286 , G11C19/00 , G11C19/184
Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.
Abstract translation: 移位寄存器包括移位寄存器单元，其中至少一个移位寄存器单元耦合到林格移位寄存器单元和后级移位寄存器单元，其中至少一个移位寄存器单元包括信号输入电路，信号输出 电路，下拉电路和开关电路。 电连接到林间移位寄存器单元的信号输入电路可以从林格移位寄存器接收逻辑信号。 信号输出电路经由控制信号端子电耦合到信号输入电路，并且电耦合到后级移位寄存器单元。 信号输出电路可以接收第一时钟信号。 下拉电路通过开关电路与控制信号端子电耦合或电隔离。
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公开(公告)号：US20160155403A1
公开(公告)日：2016-06-02
申请号：US14710605
申请日：2015-05-13
Applicant: AU Optronics Corp.
Inventor： Nan-Ying Lin , Chung-Lin Fu , Yu-Hsin Ting
IPC: G09G3/36
CPC classification number: G09G3/006 , G09G3/36 , G09G2330/12
Abstract: A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and N switches. N is a positive integer. The signal pads are configured to receive a test data signal, a voltage signal, an enable signal and a plurality of first switch control signals. The first data distributor distributes the test data signal to N output terminals of the first data distributor. Each of the logic circuit units generates a second switch control signal according to the voltage signal, the enable signal and a corresponding one of the first switch control signals. Each of the switches controls the electrical connection between an output terminal of the first data distributor coupled thereto and at least a data line coupled thereto.
Abstract translation: 提供了一种液晶显示器及其测试电路。 测试电路具有多个信号焊盘，第一数据分配器，多个逻辑电路单元和N个开关。 N是正整数。 信号焊盘被配置为接收测试数据信号，电压信号，使能信号和多个第一开关控制信号。 第一数据分配器将测试数据信号分配给第一数据分配器的N个输出端。 每个逻辑电路单元根据电压信号，使能信号和第一开关控制信号中的相应一个产生第二开关控制信号。 每个开关控制与其耦合的第一数据分配器的输出端与至少与其耦合的数据线之间的电连接。
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