公开(公告)号：US09318064B2

公开(公告)日：2016-04-19

申请号：US13661239

申请日：2012-10-26

Applicant: AU OPTRONICS CORP.

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: G09G3/36 ,  G11C19/00 ,  G09G3/38 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/38 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/184

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract translation: 移位寄存器包括移位寄存器单元，其中至少一个移位寄存器单元耦合到林格移位寄存器单元和后级移位寄存器单元，其中至少一个移位寄存器单元包括信号输入电路，信号输出 电路，下拉电路和开关电路。 电连接到林间移位寄存器单元的信号输入电路可以从林格移位寄存器接收逻辑信号。 信号输出电路经由控制信号端子电耦合到信号输入电路，并且电耦合到后级移位寄存器单元。 输出到电路的信号可以接收第一个时钟信号。 下拉电路通过开关电路与控制信号端子电耦合或电隔离。

公开(公告)号：US09847138B2

公开(公告)日：2017-12-19

申请号：US15061160

申请日：2016-03-04

Applicant: AU OPTRONICS CORP.

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: G09G3/36 ,  G11C19/28 ,  G11C19/00 ,  G09G3/38 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/38 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/184

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.