公开(公告)号：US09847138B2

公开(公告)日：2017-12-19

申请号：US15061160

申请日：2016-03-04

Applicant: AU OPTRONICS CORP.

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: G09G3/36 ,  G11C19/28 ,  G11C19/00 ,  G09G3/38 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/38 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/184

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

公开(公告)号：US09318064B2

公开(公告)日：2016-04-19

申请号：US13661239

申请日：2012-10-26

Applicant: AU OPTRONICS CORP.

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: G09G3/36 ,  G11C19/00 ,  G09G3/38 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/38 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/184

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract translation: 移位寄存器包括移位寄存器单元，其中至少一个移位寄存器单元耦合到林格移位寄存器单元和后级移位寄存器单元，其中至少一个移位寄存器单元包括信号输入电路，信号输出 电路，下拉电路和开关电路。 电连接到林间移位寄存器单元的信号输入电路可以从林格移位寄存器接收逻辑信号。 信号输出电路经由控制信号端子电耦合到信号输入电路，并且电耦合到后级移位寄存器单元。 输出到电路的信号可以接收第一个时钟信号。 下拉电路通过开关电路与控制信号端子电耦合或电隔离。

公开(公告)号：US20150235602A1

公开(公告)日：2015-08-20

申请号：US14483164

申请日：2014-09-11

Applicant: AU Optronics Corp.

Inventor： Hang-Chang Tseng ,  Nan-Ying Lin ,  Chung-Lung Li ,  Fu-Yuan Liou ,  Chung-Lin Fu

IPC: G09G3/36

CPC classification number: G09G3/3622 ,  G09G3/2018 ,  G09G2300/0426 ,  G09G2310/027 ,  G09G2340/0457

Abstract: An image display method of a half-source-driving (HSD) liquid crystal display (LCD) for mitigating the screen flickering effect caused by applying a frame rate control (FRC) algorithm in the LCD includes providing a first gate sequence corresponding to a pixel array in the LCD display. If a target gray level of the pixel array is an average value of a first gray level and a second gray level, write the first gray level to a plurality of sub-pixels of the pixel array being charged first according to the first gate sequence, and write the second gray level smaller than the first gray level to a plurality of sub-pixels of the pixel array being charged latter according to the first gate sequence.

Abstract translation: 用于减轻在LCD中应用帧速率控制（FRC）算法所引起的屏幕闪烁效应的半源驱动（HSD）液晶显示器（LCD）的图像显示方法包括提供对应于像素的第一门序列 阵列在LCD显示屏上。 如果像素阵列的目标灰度级是第一灰度级和第二灰度级的平均值，则将第一灰度级按照第一栅极序列首先写入被补充的像素阵列的多个子像素， 并且将比第一灰度级小的第二灰度级写入根据第一门序列而被加电的像素阵列的多个子像素。

公开(公告)号：US09905144B2

公开(公告)日：2018-02-27

申请号：US14710605

申请日：2015-05-13

Applicant: AU Optronics Corp.

Inventor： Nan-Ying Lin ,  Chung-Lin Fu ,  Yu-Hsin Ting

IPC: G09G3/00 ,  G09G3/36

CPC classification number: G09G3/006 ,  G09G3/36 ,  G09G2330/12

Abstract: A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and N switches. N is a positive integer. The signal pads are configured to receive a test data signal, a voltage signal, an enable signal and a plurality of first switch control signals. The first data distributor distributes the test data signal to N output terminals of the first data distributor. Each of the logic circuit units generates a second switch control signal according to the voltage signal, the enable signal and a corresponding one of the first switch control signals. Each of the switches controls the electrical connection between an output terminal of the first data distributor coupled thereto and at least a data line coupled thereto.

公开(公告)号：US09400566B2

公开(公告)日：2016-07-26

申请号：US14062381

申请日：2013-10-24

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Chun Hsu ,  Yu-Hsin Ting ,  Wei-Chih Lee ,  Chung-Lin Fu ,  Nan-Ying Lin

IPC: G09G3/36 ,  G06F3/03

CPC classification number: G06F3/03 ,  G09G3/3614 ,  G09G3/3655 ,  G09G2310/06

Abstract: A driving method for a display panel is provided. The display panel includes at least a first common signal line, at least a second common signal line and a plurality of pixels arranged as a pixel array. The pixel array includes a first pixel row and a second pixel row electrically connected to the first common signal line and the second common signal line, respectively. The driving method includes steps of: generating a first AC common signal; generating a second AC common signal, wherein the first AC common signal and the second AC common signal are inverse to each other; and providing the first and second AC common signal to the first and second pixel rows through the first and second common signal lines, respectively, by way of N-frame switch, wherein N is a positive integer.

Abstract translation: 提供了一种用于显示面板的驱动方法。 显示面板至少包括第一公共信号线，至少第二公共信号线和排列成像素阵列的多个像素。 像素阵列包括分别电连接到第一公共信号线和第二公共信号线的第一像素行和第二像素行。 驱动方法包括以下步骤：产生第一AC公共信号; 产生第二AC公共信号，其中所述第一AC公共信号和所述第二AC公共信号彼此相反; 以及通过N帧开关分别通过第一和第二公共信号线将第一和第二AC公共信号提供给第一和第二像素行，其中N是正整数。

公开(公告)号：US20160189798A1

公开(公告)日：2016-06-30

申请号：US15061160

申请日：2016-03-04

Applicant: AU OPTRONICS CORP.

Inventor： Pei-Hua CHEN ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/38 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/184

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract translation: 移位寄存器包括移位寄存器单元，其中至少一个移位寄存器单元耦合到林格移位寄存器单元和后级移位寄存器单元，其中至少一个移位寄存器单元包括信号输入电路，信号输出 电路，下拉电路和开关电路。 电连接到林间移位寄存器单元的信号输入电路可以从林格移位寄存器接收逻辑信号。 信号输出电路经由控制信号端子电耦合到信号输入电路，并且电耦合到后级移位寄存器单元。 信号输出电路可以接收第一时钟信号。 下拉电路通过开关电路与控制信号端子电耦合或电隔离。

公开(公告)号：US20160155403A1

公开(公告)日：2016-06-02

申请号：US14710605

申请日：2015-05-13

Applicant: AU Optronics Corp.

Inventor： Nan-Ying Lin ,  Chung-Lin Fu ,  Yu-Hsin Ting

IPC: G09G3/36

CPC classification number: G09G3/006 ,  G09G3/36 ,  G09G2330/12

Abstract: A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and N switches. N is a positive integer. The signal pads are configured to receive a test data signal, a voltage signal, an enable signal and a plurality of first switch control signals. The first data distributor distributes the test data signal to N output terminals of the first data distributor. Each of the logic circuit units generates a second switch control signal according to the voltage signal, the enable signal and a corresponding one of the first switch control signals. Each of the switches controls the electrical connection between an output terminal of the first data distributor coupled thereto and at least a data line coupled thereto.

Abstract translation: 提供了一种液晶显示器及其测试电路。 测试电路具有多个信号焊盘，第一数据分配器，多个逻辑电路单元和N个开关。 N是正整数。 信号焊盘被配置为接收测试数据信号，电压信号，使能信号和多个第一开关控制信号。 第一数据分配器将测试数据信号分配给第一数据分配器的N个输出端。 每个逻辑电路单元根据电压信号，使能信号和第一开关控制信号中的相应一个产生第二开关控制信号。 每个开关控制与其耦合的第一数据分配器的输出端与至少与其耦合的数据线之间的电连接。