Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES

    公开(公告)号:US20180151344A1

    公开(公告)日:2018-05-31

    申请号:US15703241

    申请日:2017-09-13

    摘要: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

    Si precursors for deposition of SiN at low temperatures

    公开(公告)号:US11289327B2

    公开(公告)日:2022-03-29

    申请号:US16574542

    申请日:2019-09-18

    摘要: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

    Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES

    公开(公告)号:US20210082684A1

    公开(公告)日:2021-03-18

    申请号:US17101428

    申请日:2020-11-23

    IPC分类号: H01L21/02

    摘要: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

    Si precursors for deposition of SiN at low temperatures
    5.
    发明授权
    Si precursors for deposition of SiN at low temperatures 有权
    Si前体,用于在低温下沉积SiN

    公开(公告)号:US09564309B2

    公开(公告)日:2017-02-07

    申请号:US14167904

    申请日:2014-01-29

    IPC分类号: H01L21/02 H01L21/311

    摘要: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

    摘要翻译: 提供了通过原子层沉积(ALD)沉积氮化硅膜的方法和前体。 在一些实施方案中,硅前体包含碘配体。 当沉积到诸如FinFETS或其它类型的多栅极FET的三维结构上时,氮化硅膜可以具有相对均匀的垂直和水平部分的蚀刻速率。 在一些实施方案中,本公开的各种氮化硅膜具有小于具有稀释HF(0.5%)的热氧化物去除速率的一半的蚀刻速率。

    Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES
    6.
    发明申请
    Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES 有权
    Si在低温下沉积SiN的前驱体

    公开(公告)号:US20140273528A1

    公开(公告)日:2014-09-18

    申请号:US13830084

    申请日:2013-03-14

    IPC分类号: H01L21/02

    摘要: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

    摘要翻译: 提供了通过原子层沉积(ALD)沉积氮化硅膜的方法和前体。 在一些实施方案中,硅前体包含碘配体。 当沉积到诸如FinFETS或其它类型的多栅极FET的三维结构上时,氮化硅膜可以具有相对均匀的垂直和水平部分的蚀刻速率。 在一些实施方案中,本公开的各种氮化硅膜具有小于热稀释HF(0.5%)的热氧化物去除速率的一半的蚀刻速率。