公开(公告)号：US20130132737A1

公开(公告)日：2013-05-23

申请号：US13627209

申请日：2012-09-26

Applicant: ARM LIMITED

Inventor： Matthew James HORSNELL ,  Richard Roy GRISENTHWAITE ,  Daniel KERSHAW ,  Stuart David BILES

IPC: G06F9/30 ,  G06F21/60

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/12 ,  H04L2209/125

Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

公开(公告)号：US20150100755A1

公开(公告)日：2015-04-09

申请号：US14461664

申请日：2014-08-18

Applicant: ARM LIMITED

Inventor： Alastair David REID ,  Daniel KERSHAW

IPC: G06F9/30 ,  G06F15/78

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/30065 ,  G06F9/45533 ,  G06F15/78

Abstract: A data processing apparatus and a method of controlling performance of speculative vector operations are provided. The apparatus comprises processing circuitry for performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements, and speculation control circuitry for maintaining a speculation width indication indicating the number of vector elements of each vector operand to be subjected to the speculative vector operations. The speculation width indication is set to an initial value prior to performance of the sequence of speculative vector operations. The processing circuitry generates progress indications during performance of the sequence of speculative vector operations, and the speculation control circuitry detects, with reference to the progress indications and speculation reduction criteria, presence of a speculation reduction condition. The speculation reduction condition is a condition indicating that a reduction in the speculation width indication is expected to improve at least one performance characteristic of the data processing apparatus relative to continued operation without the reduction in the speculation width indication. The speculation control circuitry is responsive to detection of the speculation reduction condition to reduce the speculation width indication. This can significantly increase performance (for example in terms of throughput and/or energy consumption) when performing speculative vector operations.

Abstract translation: 提供了一种数据处理装置和控制推测矢量操作性能的方法。 该装置包括用于对向量操作数执行推测向量操作序列的处理电路，每个向量操作数包括多个向量元素，以及用于维持表示每个向量操作数要承受的向量元素的数量的推测宽度指示的推测控制电路 到投机向量操作。 推测宽度指示在执行推测向量操作序列之前设置为初始值。 处理电路在执行推测向量操作的序列期间产生进展指示，并且推测控制电路参考进度指示和推测减少标准来检测存在推测减少条件。 推测减少条件是指示预测在不减少投机宽度指示的情况下预测投机宽度指示的减小将相对于继续操作来改善数据处理装置的至少一个性能特征的条件。 投机控制电路响应于推测减少条件的检测以减少投机宽度指示。 当执行推测向量操作时，这可以显着提高性能（例如在吞吐量和/或能量消耗方面）。

公开(公告)号：US20140223229A1

公开(公告)日：2014-08-07

申请号：US14246162

申请日：2014-04-07

Applicant: ARM Limited

Inventor： Emre OZER ,  Yiannakis SAZEIDES ,  Daniel KERSHAW ,  Stuart David BILES

IPC: G06F11/14

CPC classification number: G06F11/1415 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0787 ,  G06F2201/86

Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.

Abstract translation: 数据处理装置具有驻留在装置内的不同物理位置的多个存储元件，以及故障历史电路，用于检测每个存储元件中发生的局部瞬态故障，并且用于基于检测到的局部瞬态故障来维护全局瞬态故障历史数据。 分析电路监视全局瞬态故障历史数据，以基于预定标准确定全局瞬态故障历史数据是否表示在数据处理装置内发生的随机瞬态故障，或指示协调的瞬时故障攻击。 分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。 这提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图绕过数据处理设备的安全性时发起的协调的瞬态故障攻击。

公开(公告)号：US20160026806A1

公开(公告)日：2016-01-28

申请号：US14792796

申请日：2015-07-07

Applicant: ARM Limited

Inventor： Matthew James HORSNELL ,  Richard Roy GRISENTHWAITE ,  Stuart David BILES ,  Daniel KERSHAW

IPC: G06F21/60 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/12 ,  H04L2209/125

Abstract: A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Abstract translation: 数据处理系统包括单指令多数据寄存器文件和单指令多处理电路。 单指令多数据处理电路支持执行用于执行散列算法部分的密码处理指令。 操作数存储在单指令多数据寄存器文件中。 加密支持指令不遵循正常的基于通道的处理，并且生成输出操作数，其中输出操作数的不同部分取决于输入操作数中的多个不同元素。

公开(公告)号：US20150100754A1

公开(公告)日：2015-04-09

申请号：US14462194

申请日：2014-08-18

Applicant: ARM LIMITED

Inventor： Alastair David REID ,  Daniel KERSHAW

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F15/7867 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3875

Abstract: A data processing apparatus and method for performing speculative vector access operations are provided. The data processing apparatus has a reconfigurable buffer accessible to vector data access circuitry and comprising a storage array for storing up to M vectors of N vectors elements. The vector data access circuitry performs speculative data write operations in order to cause vector elements from selected vector operands in a vector register bank to be stored into the reconfigurable buffer. On occurrence of a commit condition, the vector elements currently stored in the reconfigurable buffer are then written to a data store. Speculation control circuitry maintains a speculation width indication indicating the number of vector elements of each selected vector operand stored in the reconfigurable buffer. The speculation width indication is initialised to an initial value, but on detection of an overflow condition within the reconfigurable buffer the speculation width indication is modified to reduce the number of vector elements of each selected vector operand stored in the reconfigurable buffer. The reconfigurable buffer then responds to a change in the speculation width indication by reconfiguring the storage array to increase the number of vectors M and reduce the number of vector elements N per vector. This provides an efficient mechanism for supporting performance of speculative data write operations.

Abstract translation: 提供了一种用于执行推测向量访问操作的数据处理装置和方法。 数据处理装置具有可访问向量数据访问电路的可重构缓冲器，并且包括用于存储N个向量元素的多达M个向量的存储阵列。 向量数据访问电路执行推测性数据写入操作，以便使来自向量寄存器组中的所选向量操作数的向量元素被存储到可重构缓冲器中。 在发生提交条件时，当前存储在可重构缓冲器中的向量元素然后被写入数据存储。 投机控制电路维持指示宽度指示，指示存储在可重构缓冲器中的每个所选向量操作数的向量元素的数量。 推测宽度指示初始化为初始值，但是通过检测可重构缓冲器内的溢出条件，可以修改推测宽度指示，以减少存储在可重构缓冲器中的每个选定向量操作数的向量元素的数量。 然后，可重构缓冲器通过重新配置存储阵列来响应推测宽度指示的变化，以增加向量M的数量并减少每个向量的向量元素N的数量。 这提供了一种有效的机制来支持投机数据写入操作的性能。

公开(公告)号：US20150121036A1

公开(公告)日：2015-04-30

申请号：US14585900

申请日：2014-12-30

Applicant: ARM LIMITED

Inventor： Matthew James HORSNELL ,  Richard Roy GRISENTHWAITE ,  Stuart David BILES ,  Daniel KERSHAW

IPC: G06F9/30

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/12 ,  H04L2209/125

Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Abstract translation: 数据处理系统2包括单指令多数据寄存器文件12和单指令多处理电路14.单指令多数据处理电路14支持执行用于执行散列算法部分的密码处理指令。 操作数存储在单指令多数据寄存器文件12中。加密支持指令不遵循正常的基于通道的处理，并且生成输出操作数，其中输出操作数的不同部分取决于输入操作数中的多个不同元素。