公开(公告)号：US12067399B2

公开(公告)日：2024-08-20

申请号：US17590719

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3806 ,  G06F9/3844

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US11809874B2

公开(公告)日：2023-11-07

申请号：US17590722

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia ,  Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30058 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3885

Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.

公开(公告)号：US11630771B2

公开(公告)日：2023-04-18

申请号：US17373814

申请日：2021-07-13

Applicant: APPLE INC.

Inventor： John D Pape ,  Mahesh K Reddy ,  Prasanna Utchani Varadharajan ,  Pruthivi Vuyyuru

IPC: G06F12/0802

Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.

公开(公告)号：US20230017473A1

公开(公告)日：2023-01-19

申请号：US17373814

申请日：2021-07-13

Applicant: APPLE INC.

Inventor： John D. Pape ,  Mahesh K. Reddy ,  Prasanna Utchani Varadharajan ,  Pruthivi Vuyyuru

IPC: G06F12/0802

Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.

公开(公告)号：US12236244B1

公开(公告)日：2025-02-25

申请号：US17810253

申请日：2022-06-30

Applicant: Apple Inc.

Inventor： Wei-Han Lien ,  Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Niket K. Choudhary ,  Pruthivi Vuyyuru

IPC: G06F9/38

Abstract: A multi-degree branch predictor is disclosed. A processing circuit includes an instruction fetch circuit configured to fetch branch instructions, and a branch prediction circuit having a plurality of prediction subcircuits. The prediction subcircuits are configured to store different amounts of branch history data with respect to other ones, and to receive an indication of a given branch instruction in a particular clock cycle. The prediction subcircuits implement a common branch prediction scheme to output, in different clock cycles, corresponding predictions for the given branch instruction using the different amounts of branch history data and cause, instruction fetches to be performed by the instruction fetch circuit. The prediction subcircuits are also configured to override, in subsequent clock cycles, instruction fetches caused by prediction subcircuits with comparatively less branch history data based on contrary predictions performed in subsequent clock cycles by prediction subcircuits with more branch history data.

公开(公告)号：US20250036415A1

公开(公告)日：2025-01-30

申请号：US18358890

申请日：2023-07-25

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Pruthivi Vuyyuru ,  Ian D. Kountanis

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor may include a conditional instruction prediction tracking circuit. During fetch of a conditional instruction from memory to an instruction cache of the processor, the conditional instruction prediction tracking circuit may predict whether the conditional instruction is biased. Responsive to a prediction that the conditional instruction is biased, the conditional instruction prediction tracking circuit may cause the conditional instruction to be executed according to the predicted bias. Sometimes the conditional prediction tracking circuit may cause the conditional instruction to be re-coded such that it may be executed as an unconditional instruction.

公开(公告)号：US20250021338A1

公开(公告)日：2025-01-16

申请号：US18352326

申请日：2023-07-14

Applicant: Apple Inc.

Inventor： Muawya M. Al-Otoom ,  Niket K. Choudhary ,  Pruthivi Vuyyuru

IPC: G06F9/38

Abstract: Disclosed techniques relate to next fetch predictor circuitry configured to operate in conjunction with a trace cache. The trace cache circuitry may identify and store traces of instructions based on predicted directions of one or more control transfer instructions. Trace next fetch predictor circuitry may predict a next fetch address based on a current fetch address for a current cycle, which may include predicting a next fetch address following execution of a first trace stored in the trace cache circuitry. The first trace may include multiple fetch groups and multiple control transfer instructions. Arbitration circuitry may select from among multiple predictors and the trace next fetch predictor may have priority in response to a trace cache hit. Disclosed techniques may advantageously improve overall fetch bandwidth in the context of trace cache hits.

公开(公告)号：US20250021333A1

公开(公告)日：2025-01-16

申请号：US18352323

申请日：2023-07-14

Applicant: Apple Inc.

Inventor： Ilhyun Kim ,  Niket K. Choudhary ,  Muawya M. Al-Otoom ,  Pruthivi Vuyyuru ,  Ronald P. Hall

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed techniques relate to trace caches. Trace cache circuitry may identify traces that satisfy one or more criteria. Generally, internal branches of a trace should satisfy a threshold bias level in a particular direction. To achieve this goal, the processor may initially assume that branches meet the threshold, track their usefulness in the trace context over time, and prevent inclusion of branches that fall below a usefulness threshold (which indicates that those branches are not sufficiently biased). Branches that do not meet the threshold may be added to a Bloom filter, for example. Usefulness may be tracked during trace training, when valid in a trace cache, or both.

公开(公告)号：US20240385842A1

公开(公告)日：2024-11-21

申请号：US18774678

申请日：2024-07-16

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US20230244495A1

公开(公告)日：2023-08-03

申请号：US17590722

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ethan R. Schuchman ,  Niket K. Choudhary ,  Kulin N. Kothari ,  Haoyan Jia ,  Ian D. Kountanis ,  Douglas C. Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3861 ,  G06F9/30145 ,  G06F9/30058 ,  G06F9/30079

Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.