公开(公告)号：US11630771B2

公开(公告)日：2023-04-18

申请号：US17373814

申请日：2021-07-13

Applicant: APPLE INC.

Inventor： John D Pape ,  Mahesh K Reddy ,  Prasanna Utchani Varadharajan ,  Pruthivi Vuyyuru

IPC: G06F12/0802

Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.