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公开(公告)号：US11272618B2
公开(公告)日：2022-03-08
申请号：US16095276
申请日：2017-04-11
Inventor： John David Brazzle , Frederick E. Beville , David A. Pruitt
Abstract: A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module.
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公开(公告)号：US20200312814A1
公开(公告)日：2020-10-01
申请号：US16817203
申请日：2020-03-12
Inventor： Albert M. Wu , John David Brazzle , Zafer Kutlu
IPC: H01L25/065 , H01L23/31 , H01L21/56 , H01L25/00
Abstract: A packaging technology in which power switching elements, such as field-effect transistors (FETs), can be oriented in a vertical position relative to the printed circuit board (PCB) on which the product is mounted. The power die including the switching element(s) can essentially stand “on end” so that they take up very little PCB area. Multiple dies can be positioned this way, and the dies can be attached to a heat sink structure, which is designed to take the heat generated by the dies onto the top of the package. The heat sink structure can be attached to a structure to route the power and analog signals properly to the desired pins/leads/balls of the finished product. Using these techniques can result in a significant increase in the power density (both PCB space and solution volume) of power switching elements, e.g., FETs.
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公开(公告)号：US11844178B2
公开(公告)日：2023-12-12
申请号：US17325080
申请日：2021-05-19
Inventor： John David Brazzle , Sok Mun Chew
CPC classification number: H05K1/181 , H01F27/29 , H01L23/3121 , H01L25/167 , H05K3/3447 , H01L23/49575 , H05K2201/1003 , H05K2201/10515 , H05K2201/10901
Abstract: An electronic device and a method of forming such an electronic device are disclosed. The electronic device can include an integrated device package and a component. The integrated device package includes a substrate and a package body over the substrate, and a hole formed through the package body to expose a conductive pad of the substrate. The component is mounted over the package body, and includes a component body and a lead extending from the component body through the hole. The lead includes an insulated portion and a distal exposed portion, and the insulated portion includes a conductor and an insulating layer disposed about the conductor, wherein the distal exposed portion is uncovered by the insulating layer such that the conductor is exposed at the distal portion. The electronic device can also include a conductive material that electrically connects the distal exposed portion to the conductive pad of the substrate.
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公开(公告)号：US11476232B2
公开(公告)日：2022-10-18
申请号：US16817203
申请日：2020-03-12
Inventor： Albert M. Wu , John David Brazzle , Zafer Kutlu
IPC: H01L25/065 , H01L25/00 , H01L21/56 , H01L23/31
Abstract: A packaging technology in which power switching elements, such as field-effect transistors (FETs), can be oriented in a vertical position relative to the printed circuit board (PCB) on which the product is mounted. The power die including the switching element(s) can essentially stand “on end” so that they take up very little PCB area. Multiple dies can be positioned this way, and the dies can be attached to a heat sink structure, which is designed to take the heat generated by the dies onto the top of the package. The heat sink structure can be attached to a structure to route the power and analog signals properly to the desired pins/leads/balls of the finished product. Using these techniques can result in a significant increase in the power density (both PCB space and solution volume) of power switching elements, e.g., FETs.
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