公开(公告)号：US09286111B2

公开(公告)日：2016-03-15

申请号：US13870145

申请日：2013-04-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Martin T. Pohlack ,  Stephan Diestelhorst

IPC: G06F9/46 ,  G06F7/38

CPC classification number: G06F9/466 ,  G06F9/467

Abstract: The described embodiments include a processor that handles operations during transactions. In these embodiments, the processor comprises one or more cores. During operation, at least one core is configured to monitor the acquisition of time stamps during transactions. The at least one core is further configured to prevent the acquisition of time stamps that meet predetermined conditions.

Abstract translation: 所描述的实施例包括处理事务期间的操作的处理器。 在这些实施例中，处理器包括一个或多个核。 在操作期间，至少一个核心被配置为监视在交易期间获取时间戳。 所述至少一个核还被配置为防止获取满足预定条件的时间戳。

公开(公告)号：US09916189B2

公开(公告)日：2018-03-13

申请号：US14479297

申请日：2014-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Martin T. Pohlack ,  Stephan Diestelhorst

IPC: G06F9/52 ,  G06F12/06 ,  G06F9/45 ,  G06F12/0855

CPC classification number: G06F9/52 ,  G06F8/458 ,  G06F12/0857 ,  G06F2201/825

Abstract: In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.

公开(公告)号：US20160070659A1

公开(公告)日：2016-03-10

申请号：US14479297

申请日：2014-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Martin T. Pohlack ,  Stephan Diestelhorst

IPC: G06F12/14 ,  G06F12/08

CPC classification number: G06F9/52 ,  G06F8/458 ,  G06F12/0857 ,  G06F2201/825

Abstract: In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.

Abstract translation: 在所描述的实施例中，计算设备中的实体选择性地将指定的值写入本地高速缓存中的锁定变量和存储器层次结构的一个或多个较低级别，以使得多个实体能够同时执行相应的程序代码的关键部分， 由同一个锁保护。

公开(公告)号：US20150205721A1

公开(公告)日：2015-07-23

申请号：US14160552

申请日：2014-01-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephan Diestelhorst ,  Martin T. Pohlack ,  Michael P. Hohmuth

IPC: G06F12/08 ,  G06F9/46

CPC classification number: G06F12/0811

Abstract: The described embodiments include a computing device that handles cache blocks during a transaction. In the described embodiments, after an entity has written to a cache block in a cache during the transaction, the computing device responds to a read request for the cache block from another entity with a copy of the cache block in a pre-transactional state. In these embodiments, the entity executing the transaction continues the transaction after the computing device responds to the read request from the other entity.

Abstract translation: 所描述的实施例包括在事务期间处理高速缓存块的计算设备。 在所描述的实施例中，在事务中实体已经写入高速缓存中的高速缓存块之后，计算设备响应来自另一实体的高速缓存块的读取请求，其中高速缓存块的副本处于事务前状态。 在这些实施例中，执行事务的实体在计算设备响应来自另一实体的读取请求之后继续进行事务。

公开(公告)号：US20130290965A1

公开(公告)日：2013-10-31

申请号：US13870145

申请日：2013-04-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Martin T. Pohlack ,  Stephan Diestelhorst

IPC: G06F9/46

CPC classification number: G06F9/466 ,  G06F9/467

Abstract: The described embodiments include a processor that handles operations during transactions. In these embodiments, the processor comprises one or more cores. During operation, at least one core is configured to monitor the acquisition of time stamps during transactions. The at least one core is further configured to prevent the acquisition of time stamps that meet predetermined conditions.

Abstract translation: 所描述的实施例包括处理事务期间的操作的处理器。 在这些实施例中，处理器包括一个或多个核。 在操作期间，至少一个核心被配置为监视在交易期间获取时间戳。 所述至少一个核还被配置为防止获取满足预定条件的时间戳。